diff for duplicates of <20141113110002.GE20652@localhost> diff --git a/a/1.txt b/N1/1.txt index 7d112af..8aeaf15 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -3,7 +3,7 @@ On Tue, Nov 11, 2014 at 01:24:39AM +0000, Suravee Suthikulpanit wrote: Let's cc the arm-soc guys, they are now handling SoC code for arm64. -> On 10/28/14 20:36, suravee.suthikulpanit at amd.com wrote: +> On 10/28/14 20:36, suravee.suthikulpanit@amd.com wrote: > > From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> > > > > Initial revision of device tree for AMD Seattle platform @@ -118,7 +118,7 @@ Let's cc the arm-soc guys, they are now handling SoC code for arm64. > > + clock-output-names = "uartspiclk_100mhz"; > > + }; > > + -> > + dma0: dma at 0500000 { +> > + dma0: dma@0500000 { > > + compatible = "arm,pl330", "arm,primecell"; > > + reg = <0 0x0500000 0 0x1000>; > > + interrupts = @@ -135,7 +135,7 @@ Let's cc the arm-soc guys, they are now handling SoC code for arm64. > > + #dma-cells = <1>; > > + }; > > + -> > + sata0: sata at 00300000 { +> > + sata0: sata@00300000 { > > + compatible = "snps,dwc-ahci"; > > + reg = <0 0x300000 0 0x800>; > > + interrupts = <0 355 4>; @@ -144,7 +144,7 @@ Let's cc the arm-soc guys, they are now handling SoC code for arm64. > > + dma-coherent; > > + }; > > + -> > + i2c at 1000000 { +> > + i2c@1000000 { > > + compatible = "snps,designware-i2c"; > > + reg = <0 0x01000000 0 0x1000>; > > + interrupts = <0 357 4>; @@ -152,7 +152,7 @@ Let's cc the arm-soc guys, they are now handling SoC code for arm64. > > + clock-names = "apb_pclk"; > > + }; > > + -> > + serial0: serial at 1010000 { +> > + serial0: serial@1010000 { > > + compatible = "arm,pl011", "arm,primecell"; > > + reg = <0 0x1010000 0 0x1000>; > > + interrupts = <0 328 4>; @@ -160,7 +160,7 @@ Let's cc the arm-soc guys, they are now handling SoC code for arm64. > > + clock-names = "uartclk", "apb_pclk"; > > + }; > > + -> > + ssp at 1020000 { +> > + ssp@1020000 { > > + compatible = "arm,pl022", "arm,primecell"; > > + #gpio-cells = <2>; > > + reg = <0 0x1020000 0 0x1000>; @@ -170,7 +170,7 @@ Let's cc the arm-soc guys, they are now handling SoC code for arm64. > > + clock-names = "apb_pclk"; > > + }; > > + -> > + ssp at 1030000 { +> > + ssp@1030000 { > > + compatible = "arm,pl022", "arm,primecell"; > > + #gpio-cells = <2>; > > + reg = <0 0x1030000 0 0x1000>; @@ -182,7 +182,7 @@ Let's cc the arm-soc guys, they are now handling SoC code for arm64. > > + #address-cells = <1>; > > + #size-cells = <0>; > > + -> > + sdcard at 0 { +> > + sdcard@0 { > > + compatible = "mmc-spi-slot"; > > + reg = <0>; > > + spi-max-frequency = <20000000>; @@ -194,7 +194,7 @@ Let's cc the arm-soc guys, they are now handling SoC code for arm64. > > + }; > > + }; > > + -> > + gpio0: gpio at 1040000 { +> > + gpio0: gpio@1040000 { > > + compatible = "arm,pl061", "arm,primecell"; > > + #gpio-cells = <2>; > > + reg = <0 0x1040000 0 0x1000>; @@ -204,7 +204,7 @@ Let's cc the arm-soc guys, they are now handling SoC code for arm64. > > + clock-names = "apb_pclk"; > > + }; > > + -> > + gpio1: gpio at 1050000 { +> > + gpio1: gpio@1050000 { > > + compatible = "arm,pl061", "arm,primecell"; > > + #gpio-cells = <2>; > > + reg = <0 0x1050000 0 0x1000>; @@ -214,7 +214,7 @@ Let's cc the arm-soc guys, they are now handling SoC code for arm64. > > + clock-names = "apb_pclk"; > > + }; > > + -> > + ccp: ccp at 00100000 { +> > + ccp: ccp@00100000 { > > + compatible = "amd,ccp-seattle-v1a"; > > + reg = <0 0x00100000 0 0x10000>; > > + interrupts = <0 3 4>; @@ -246,7 +246,7 @@ Let's cc the arm-soc guys, they are now handling SoC code for arm64. > > + linux,pci-probe-only; > > + }; > > + -> > + gic: interrupt-controller at e1101000 { +> > + gic: interrupt-controller@e1101000 { > > + compatible = "arm,gic-400", "arm,cortex-a15-gic"; > > + interrupt-controller; > > + #interrupt-cells = <3>; @@ -258,7 +258,7 @@ Let's cc the arm-soc guys, they are now handling SoC code for arm64. > > + <0x0 0xe1160000 0 0x10000>; > > + interrupts = <1 8 0xf04>; > > + ranges; -> > + v2m0: v2m at e1180000 { +> > + v2m0: v2m@e1180000 { > > + compatible = "arm,gic-v2m-frame"; > > + msi-controller; > > + arm,msi-base-spi = <64>; diff --git a/a/content_digest b/N1/content_digest index cfcde33..c8082bb 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,18 @@ "ref\01414503414-3863-1-git-send-email-suravee.suthikulpanit@amd.com\0" "ref\054616557.1010403@amd.com\0" - "From\0catalin.marinas@arm.com (Catalin Marinas)\0" - "Subject\0[PATCH V3] arm64: amd-seattle: Adding device tree for AMD Seattle platform\0" + "From\0Catalin Marinas <catalin.marinas@arm.com>\0" + "Subject\0Re: [PATCH V3] arm64: amd-seattle: Adding device tree for AMD Seattle platform\0" "Date\0Thu, 13 Nov 2014 11:00:03 +0000\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>\0" + "Cc\0Mark Rutland <Mark.Rutland@arm.com>" + Will Deacon <Will.Deacon@arm.com> + Marc Zyngier <Marc.Zyngier@arm.com> + Liviu Dudau <Liviu.Dudau@arm.com> + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + Thomas Lendacky <Thomas.Lendacky@amd.com> + Joel Schopp <Joel.Schopp@amd.com> + " arm@kernel.org\0" "\00:1\0" "b\0" "On Tue, Nov 11, 2014 at 01:24:39AM +0000, Suravee Suthikulpanit wrote:\n" @@ -11,7 +20,7 @@ "\n" "Let's cc the arm-soc guys, they are now handling SoC code for arm64.\n" "\n" - "> On 10/28/14 20:36, suravee.suthikulpanit at amd.com wrote:\n" + "> On 10/28/14 20:36, suravee.suthikulpanit@amd.com wrote:\n" "> > From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>\n" "> >\n" "> > Initial revision of device tree for AMD Seattle platform\n" @@ -126,7 +135,7 @@ "> > + clock-output-names = \"uartspiclk_100mhz\";\n" "> > + };\n" "> > +\n" - "> > + dma0: dma at 0500000 {\n" + "> > + dma0: dma@0500000 {\n" "> > + compatible = \"arm,pl330\", \"arm,primecell\";\n" "> > + reg = <0 0x0500000 0 0x1000>;\n" "> > + interrupts =\n" @@ -143,7 +152,7 @@ "> > + #dma-cells = <1>;\n" "> > + };\n" "> > +\n" - "> > + sata0: sata at 00300000 {\n" + "> > + sata0: sata@00300000 {\n" "> > + compatible = \"snps,dwc-ahci\";\n" "> > + reg = <0 0x300000 0 0x800>;\n" "> > + interrupts = <0 355 4>;\n" @@ -152,7 +161,7 @@ "> > + dma-coherent;\n" "> > + };\n" "> > +\n" - "> > + i2c at 1000000 {\n" + "> > + i2c@1000000 {\n" "> > + compatible = \"snps,designware-i2c\";\n" "> > + reg = <0 0x01000000 0 0x1000>;\n" "> > + interrupts = <0 357 4>;\n" @@ -160,7 +169,7 @@ "> > + clock-names = \"apb_pclk\";\n" "> > + };\n" "> > +\n" - "> > + serial0: serial at 1010000 {\n" + "> > + serial0: serial@1010000 {\n" "> > + compatible = \"arm,pl011\", \"arm,primecell\";\n" "> > + reg = <0 0x1010000 0 0x1000>;\n" "> > + interrupts = <0 328 4>;\n" @@ -168,7 +177,7 @@ "> > + clock-names = \"uartclk\", \"apb_pclk\";\n" "> > + };\n" "> > +\n" - "> > + ssp at 1020000 {\n" + "> > + ssp@1020000 {\n" "> > + compatible = \"arm,pl022\", \"arm,primecell\";\n" "> > + #gpio-cells = <2>;\n" "> > + reg = <0 0x1020000 0 0x1000>;\n" @@ -178,7 +187,7 @@ "> > + clock-names = \"apb_pclk\";\n" "> > + };\n" "> > +\n" - "> > + ssp at 1030000 {\n" + "> > + ssp@1030000 {\n" "> > + compatible = \"arm,pl022\", \"arm,primecell\";\n" "> > + #gpio-cells = <2>;\n" "> > + reg = <0 0x1030000 0 0x1000>;\n" @@ -190,7 +199,7 @@ "> > + #address-cells = <1>;\n" "> > + #size-cells = <0>;\n" "> > +\n" - "> > + sdcard at 0 {\n" + "> > + sdcard@0 {\n" "> > + compatible = \"mmc-spi-slot\";\n" "> > + reg = <0>;\n" "> > + spi-max-frequency = <20000000>;\n" @@ -202,7 +211,7 @@ "> > + };\n" "> > + };\n" "> > +\n" - "> > + gpio0: gpio at 1040000 {\n" + "> > + gpio0: gpio@1040000 {\n" "> > + compatible = \"arm,pl061\", \"arm,primecell\";\n" "> > + #gpio-cells = <2>;\n" "> > + reg = <0 0x1040000 0 0x1000>;\n" @@ -212,7 +221,7 @@ "> > + clock-names = \"apb_pclk\";\n" "> > + };\n" "> > +\n" - "> > + gpio1: gpio at 1050000 {\n" + "> > + gpio1: gpio@1050000 {\n" "> > + compatible = \"arm,pl061\", \"arm,primecell\";\n" "> > + #gpio-cells = <2>;\n" "> > + reg = <0 0x1050000 0 0x1000>;\n" @@ -222,7 +231,7 @@ "> > + clock-names = \"apb_pclk\";\n" "> > + };\n" "> > +\n" - "> > + ccp: ccp at 00100000 {\n" + "> > + ccp: ccp@00100000 {\n" "> > + compatible = \"amd,ccp-seattle-v1a\";\n" "> > + reg = <0 0x00100000 0 0x10000>;\n" "> > + interrupts = <0 3 4>;\n" @@ -254,7 +263,7 @@ "> > + linux,pci-probe-only;\n" "> > + };\n" "> > +\n" - "> > + gic: interrupt-controller at e1101000 {\n" + "> > + gic: interrupt-controller@e1101000 {\n" "> > + compatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n" "> > + interrupt-controller;\n" "> > + #interrupt-cells = <3>;\n" @@ -266,7 +275,7 @@ "> > + <0x0 0xe1160000 0 0x10000>;\n" "> > + interrupts = <1 8 0xf04>;\n" "> > + ranges;\n" - "> > + v2m0: v2m at e1180000 {\n" + "> > + v2m0: v2m@e1180000 {\n" "> > + compatible = \"arm,gic-v2m-frame\";\n" "> > + msi-controller;\n" "> > + arm,msi-base-spi = <64>;\n" @@ -358,4 +367,4 @@ "> > + };\n" > > +}; -6589e771339d7b5c3b4fb4b7583c1268b095b26df923c219936e4809b492f6ba +a4f3a58a775315e209a1f4c31bd18df032c2af2f0bda0597cd00b93eb491a01e
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