From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 6/6] x86: Use clwb in drm_clflush_virt_range Date: Thu, 13 Nov 2014 20:14:11 +0200 Message-ID: <20141113181411.GU10649@intel.com> References: <1415731396-19364-1-git-send-email-ross.zwisler@linux.intel.com> <1415731396-19364-7-git-send-email-ross.zwisler@linux.intel.com> <5464220D.6090204@amacapital.net> <20141113112017.GA14416@pd.tnic> <20141113171133.GD14070@pd.tnic> <20141113173354.GT10649@intel.com> <20141113174734.GF14070@pd.tnic> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <20141113174734.GF14070@pd.tnic> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Borislav Petkov Cc: intel-gfx@lists.freedesktop.org, X86 ML , "linux-kernel@vger.kernel.org" , DRI , Andy Lutomirski , Thomas Gleixner , Ross Zwisler , H Peter Anvin , Ingo Molnar List-Id: dri-devel@lists.freedesktop.org T24gVGh1LCBOb3YgMTMsIDIwMTQgYXQgMDY6NDc6MzRQTSArMDEwMCwgQm9yaXNsYXYgUGV0a292 IHdyb3RlOgo+IE9uIFRodSwgTm92IDEzLCAyMDE0IGF0IDA3OjMzOjU0UE0gKzAyMDAsIFZpbGxl IFN5cmrDpGzDpCB3cm90ZToKPiA+IFdlIHVzZSBpdCBib3RoIHdheXMgaW4gaTkxNS4gU28gcGxl YXNlIGRvbid0IGJyZWFrIGl0Lgo+IAo+IEhhaGEsIHdlIHN0YXJ0ZWQgZnJvbSBJbnRlbCB3aXRo IFJvc3MnIHBhdGNoIGFuZCBtYWRlIGEgZnVsbCBjaXJjbGUKPiBiYWNrLiBNYXliZSB5b3UgZ3V5 cyBzaG91bGQgdGFsayBhYm91dCBpdC4KPiAKPiBMT0wuIDotKQoKSW5kZWVkLiBUaGUgcHJvYmxl bSBJIHNlZSB3aXRoIHRoZXNlIHBhdGNoZXMgaXMgdGhhdCB0aGV5IGRvbid0IGFjdHVhbGx5CnRl bGwgd2hhdCB0aGUgbmV3IGluc3RydWN0aW9uIGRvZXMsIHNvIGEgY2FzdWFsIGdsYW5jZSBkb2Vz bid0IHJlYWxseQpyYWlzZSBhbnkgcmVkIGZsYWdzLiBBbm90aGVyIGV4Y3VzZSBJIGNhbiB1c2Ug aXMgdGhhdCBJIGp1c3QgZ290IHVzZWQKdG8gdGhlIGZhY3QgdGhhdCB0aGUgeDg2IGhhc24ndCBo aXN0b3JpY2FsbHkgYm90aGVyZWQgc2VwYXJhdGluZwppbnZhbGlkYXRlIGFuZCB3cml0ZWJhY2sg YW5kIGp1c3QgZG9lcyBib3RoLiBJbiBteSBwcmV2aW91cyBsaWZlIG9uIHRoZQpkYXJrXldhcm0g c2lkZSBJIGRpZCBhY3R1YWxseSBrbm93IHRoZSBkaWZmZXJlbmNlIDopCgpCdXQgdGhlcmUncyBw bGVudHkgb2YgYmxhbWUgdG8gZ28gYXJvdW5kIHRvIHRoZSBvdGhlciBzaWRlIG9mIHRoZSBmZW5j ZQp0b28uIFdlIHNob3VsZCBoYXZlIGRvY3VtZW50ZWQgd2hhdCB3ZSBleHBlY3QgZnJvbSB0aGVz ZSBmdW5jdGlvbnMuCkN1cnJlbnRseSB5b3UganVzdCBoYXZlIHRvIGtub3cvZ3Vlc3MsIGFuZCB0 aGF0J3MganVzdCBub3QgZ29vZCBlbm91Z2guCgotLSAKVmlsbGUgU3lyasOkbMOkCkludGVsIE9U QwpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpJbnRlbC1n ZnggbWFpbGluZyBsaXN0CkludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cDovL2xp c3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdmeAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933624AbaKMSOS (ORCPT ); Thu, 13 Nov 2014 13:14:18 -0500 Received: from mga03.intel.com ([134.134.136.65]:60239 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932610AbaKMSOR (ORCPT ); Thu, 13 Nov 2014 13:14:17 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,379,1413270000"; d="scan'208";a="607394500" Date: Thu, 13 Nov 2014 20:14:11 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Borislav Petkov Cc: Andy Lutomirski , intel-gfx@lists.freedesktop.org, X86 ML , "linux-kernel@vger.kernel.org" , DRI , Ingo Molnar , Ross Zwisler , H Peter Anvin , Thomas Gleixner Subject: Re: [PATCH 6/6] x86: Use clwb in drm_clflush_virt_range Message-ID: <20141113181411.GU10649@intel.com> References: <1415731396-19364-1-git-send-email-ross.zwisler@linux.intel.com> <1415731396-19364-7-git-send-email-ross.zwisler@linux.intel.com> <5464220D.6090204@amacapital.net> <20141113112017.GA14416@pd.tnic> <20141113171133.GD14070@pd.tnic> <20141113173354.GT10649@intel.com> <20141113174734.GF14070@pd.tnic> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20141113174734.GF14070@pd.tnic> User-Agent: Mutt/1.5.22 (2013-10-16) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 13, 2014 at 06:47:34PM +0100, Borislav Petkov wrote: > On Thu, Nov 13, 2014 at 07:33:54PM +0200, Ville Syrjälä wrote: > > We use it both ways in i915. So please don't break it. > > Haha, we started from Intel with Ross' patch and made a full circle > back. Maybe you guys should talk about it. > > LOL. :-) Indeed. The problem I see with these patches is that they don't actually tell what the new instruction does, so a casual glance doesn't really raise any red flags. Another excuse I can use is that I just got used to the fact that the x86 hasn't historically bothered separating invalidate and writeback and just does both. In my previous life on the dark^Warm side I did actually know the difference :) But there's plenty of blame to go around to the other side of the fence too. We should have documented what we expect from these functions. Currently you just have to know/guess, and that's just not good enough. -- Ville Syrjälä Intel OTC