From: Damien Lespiau <damien.lespiau@intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 00/10] SKL stage 1 part 3
Date: Fri, 14 Nov 2014 11:30:31 +0000 [thread overview]
Message-ID: <20141114113031.GA2661@strange.ger.corp.intel.com> (raw)
In-Reply-To: <20141114102036.GK25711@phenom.ffwll.local>
On Fri, Nov 14, 2014 at 11:20:36AM +0100, Daniel Vetter wrote:
> On Thu, Nov 13, 2014 at 02:55:12PM +0000, Damien Lespiau wrote:
> > Another series of reviewed patches. This time SKL clocks minus DPLL0 (eDP) and
> > a extra small patch to not apply the HSW/BDW eDP link training W/A.
>
> Pulled them all in. Tbh I haven't fully cross-checked whether this will
> conflict with the recently merged dpll rework from Ander, but also didn't
> spot anything while reading through patches.
>
> Thanks for patches&review.
I rebased them on top of the recent work from Ander, it broke of course,
but just needed a few new_config sprinkled here and there. With that, it
seems happy enough (except for eDP, but that's on its way)
--
Damien
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prev parent reply other threads:[~2014-11-14 11:30 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-13 14:55 [PATCH 00/10] SKL stage 1 part 3 Damien Lespiau
2014-11-13 14:55 ` [PATCH 01/10] drm/i915/skl: Register definitions for SKL Clocks Damien Lespiau
2014-11-13 14:55 ` [PATCH 02/10] drm/i915/skl: Structure/enum definitions for SKL clocks Damien Lespiau
2014-11-13 14:55 ` [PATCH 03/10] drm/i915/skl: CD clock back calculation for SKL Damien Lespiau
2014-11-13 14:55 ` [PATCH 04/10] drm/i915/skl: Determine enabled PLL and its linkrate/pixel clock Damien Lespiau
2014-11-13 14:55 ` [PATCH 05/10] drm/i915/skl: Query DPLL attached to port on SKL Damien Lespiau
2014-11-13 14:55 ` [PATCH 06/10] drm/i915/skl: Define shared DPLLs for Skylake Damien Lespiau
2014-11-13 14:55 ` [PATCH 07/10] drm/i915/skl: Adjust the port PLL selection code Damien Lespiau
2014-11-13 14:55 ` [PATCH 08/10] drm/i915/skl: Implementation of SKL DPLL programming Damien Lespiau
2014-11-13 14:55 ` [PATCH 09/10] drm/i915/skl: Provide skl-specific pll hw state cross-checking Damien Lespiau
2014-11-13 14:55 ` [PATCH 10/10] drm/i915/skl: Apply eDP WA only for gen < 9 Damien Lespiau
2014-11-14 0:39 ` [PATCH 10/10] drm/i915/skl: Apply eDP WA only for gen < shuang.he
2014-11-14 10:20 ` [PATCH 00/10] SKL stage 1 part 3 Daniel Vetter
2014-11-14 11:30 ` Damien Lespiau [this message]
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