From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3] drm/i915: Move to CPU domain in pwrite/pread
Date: Fri, 14 Nov 2014 20:35:57 +0200 [thread overview]
Message-ID: <20141114183557.GE10649@intel.com> (raw)
In-Reply-To: <20141114170059.GC9624@nuc-i3427.alporthouse.com>
On Fri, Nov 14, 2014 at 05:00:59PM +0000, Chris Wilson wrote:
> On Wed, Nov 12, 2014 at 11:47:14PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Currently it's possible to get visible cache dirt on scanout on LLC
> > machines when using pwrite on the future scanout bo if its cache_level
> > is already NONE.
> >
> > pwrite's "does this need clflush?" checks would decide that no clflush
> > is necessary since the bo isn't currently pinned to the display and LLC
> > makes everything else coherent. The subsequent set_cache_level(NONE)
> > would also do nothing since cache_level is already correct. And hence
> > no clflush will be performed and we flip to a bo which can still have
> > dirty data in the caches.
> >
> > To correctly track the cache dirtyness move the object to CPU write
> > domain in pwrite. This cures the cache dirt since we explicitly flush
> > the CPU write domain in the pin_to_display path.
> >
> > Give pread the same treatment simply in the name of symmetry.
> >
> > v2: Use trace_i915_gem_object_change_domain() and provide some kind
> > of commit message
> > v3: Don't mark things as clean if we're not sure everything got
> > flushed (Chris)
>
> I think we just want to be more conservative during clflushes after
> pwrite:
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 557746b2b72b..e9f98531b9d2 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -75,7 +75,7 @@ static bool cpu_cache_is_coherent(struct drm_device *dev,
>
> static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
> {
> - if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
> + if (level != I915_CACHE_NONE)
You mean == ?
And I guess you'd then have to consider WT as well.
It would mean we'd end up clflushing even when not strictly needed. But
maybe that's acceptable.
> return true;
>
> return obj->pin_display;
>
> --
> Chris Wilson, Intel Open Source Technology Centre
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2014-11-14 18:36 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <=1415804230-17732-1-git-send-email-ville.syrjala@linux.intel.com>
2014-11-12 21:47 ` [PATCH v3] drm/i915: Move to CPU domain in pwrite/pread ville.syrjala
2014-11-13 7:26 ` shuang.he
2014-11-13 15:56 ` [PATCH i-g-t] tests/kms_pwrite_crc: Add pwrite vs display coherency test ville.syrjala
2014-11-14 17:00 ` [PATCH v3] drm/i915: Move to CPU domain in pwrite/pread Chris Wilson
2014-11-14 18:35 ` Ville Syrjälä [this message]
2014-11-15 10:40 ` Chris Wilson
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