From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 01/18] drm/i915: Return more precise cdclk for gen2/3
Date: Mon, 17 Nov 2014 21:02:11 +0200 [thread overview]
Message-ID: <20141117190211.GL10649@intel.com> (raw)
In-Reply-To: <20141117184430.GJ25711@phenom.ffwll.local>
On Mon, Nov 17, 2014 at 07:44:30PM +0100, Daniel Vetter wrote:
> On Mon, Nov 17, 2014 at 04:43:35PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Fill out the lower three digits for gen2 and gen3 cdclk frqeuncy. It's
> > not clear if these are accurate frquencies or just in the ballpark, but
> > without docs this is the best we can do.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Given that no one complained yet I'm not sure this is worth the trouble.
> Otoh it's all below the 10% margin we have already anyway, so one big
> wash ;-)
Yeah <1Mhz is a fairly small error here. But I still prefer to make the
change, if only for consistency. Otherwise it'll keep bugging me and
I'll have to keep fighting the urge to change it every time I see those
numbers.
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2014-11-17 19:03 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-17 14:43 [PATCH 00/18] drm/i915: All sorts of cdclk stuff ville.syrjala
2014-11-17 14:43 ` [PATCH 01/18] drm/i915: Return more precise cdclk for gen2/3 ville.syrjala
2014-11-17 18:44 ` Daniel Vetter
2014-11-17 19:02 ` Ville Syrjälä [this message]
2014-11-17 19:13 ` Daniel Vetter
2014-11-17 14:43 ` [PATCH 02/18] drm/i915: Fix i855_get_display_clock_speed() ville.syrjala
2014-11-17 14:43 ` [PATCH 03/18] drm/i915: Fix 852GM/GMV cdclk ville.syrjala
2014-11-17 14:43 ` [PATCH 04/18] drm/i915: Add cdclk extraction for g33, 965gm and g4x ville.syrjala
2014-11-17 14:43 ` [PATCH 05/18] drm/i915: ILK cdclk seems to be 450MHz ville.syrjala
2014-11-17 14:43 ` [PATCH 06/18] drm/i915: Assume 400 MHz cdclk for the rest of gen4-7 ville.syrjala
2014-11-17 18:46 ` Daniel Vetter
2014-11-17 19:22 ` Ville Syrjälä
2014-11-17 14:43 ` [PATCH 07/18] drm/i915: Simplify ilk_get_aux_clock_divider() ville.syrjala
2014-11-17 14:43 ` [PATCH 08/18] drm/i915: Convert the ddi cdclk code to .get_display_clock_speed() ville.syrjala
2014-11-17 14:43 ` [PATCH 09/18] drm/i915: Warn when cdclk for the platforms is not known ville.syrjala
2014-11-17 14:43 ` [PATCH 10/18] drm/i915: Cache the current cdclk frequency in dev_priv ville.syrjala
2014-11-17 14:43 ` [PATCH 11/18] drm/i915: Use cached cdclk value ville.syrjala
2014-11-17 18:41 ` Daniel Vetter
2014-11-17 19:06 ` Ville Syrjälä
2014-11-17 19:09 ` Daniel Vetter
2014-11-17 14:43 ` [PATCH 12/18] drm/i915: Unify ilk and hsw .get_aux_clock_divider() ville.syrjala
2014-11-17 14:43 ` [PATCH 13/18] drm/i915: Store max cdclk value in dev_priv ville.syrjala
2014-11-17 18:43 ` Daniel Vetter
2014-11-17 19:30 ` Ville Syrjälä
2014-11-17 14:43 ` [PATCH 14/18] drm/i915: Don't enable IPS when pixel rate exceeds 95% of cdclk ville.syrjala
2014-11-17 19:02 ` Daniel Vetter
2014-11-18 0:38 ` Runyan, Arthur J
2014-11-17 14:43 ` [PATCH 15/18] drm/i915: Fix chv cdclk support ville.syrjala
2014-11-17 14:43 ` [PATCH 16/18] drm/i915: HSW cdclk change support ville.syrjala
2014-11-17 14:43 ` [PATCH 17/18] drm/i915: Add IS_BDW_ULX() ville.syrjala
2014-11-17 14:43 ` [PATCH 18/18] drm/i915: BDW cdclk change support ville.syrjala
2014-11-18 6:51 ` shuang.he
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