From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Dec 2014 23:48:33 +0100 (CET) Received: from mail.linuxfoundation.org ([140.211.169.12]:48107 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27008247AbaLEWqHrUuBx (ORCPT ); Fri, 5 Dec 2014 23:46:07 +0100 Received: from localhost (c-24-22-230-10.hsd1.wa.comcast.net [24.22.230.10]) by mail.linuxfoundation.org (Postfix) with ESMTPSA id 4F174934; Fri, 5 Dec 2014 22:45:56 +0000 (UTC) From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Markos Chandras , linux-mips@linux-mips.org, Ralf Baechle Subject: [PATCH 3.17 009/122] MIPS: r4kcache: Add EVA case for protected_writeback_dcache_line Date: Fri, 5 Dec 2014 14:43:03 -0800 Message-Id: <20141205223306.905029998@linuxfoundation.org> X-Mailer: git-send-email 2.1.3 In-Reply-To: <20141205223305.514276242@linuxfoundation.org> References: <20141205223305.514276242@linuxfoundation.org> User-Agent: quilt/0.63-1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 44602 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@linuxfoundation.org Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips 3.17-stable review patch. If anyone has any objections, please let me know. ------------------ From: Markos Chandras commit 83fd43449baaf88fe5c03dd0081a062041837c51 upstream. Commit de8974e3f76c0 ("MIPS: asm: r4kcache: Add EVA cache flushing functions") added cache function for EVA using the cachee instruction. However, it didn't add a case for the protected_writeback_dcache_line. mips_dsemul() calls r4k_flush_cache_sigtramp() which in turn uses the protected_writeback_dcache_line() to flush the trampoline code back to memory. This used the wrong "cache" instruction leading to random userland crashes on non-FPU cores. Signed-off-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8331/ Signed-off-by: Ralf Baechle Signed-off-by: Greg Kroah-Hartman --- arch/mips/include/asm/r4kcache.h | 4 ++++ 1 file changed, 4 insertions(+) --- a/arch/mips/include/asm/r4kcache.h +++ b/arch/mips/include/asm/r4kcache.h @@ -257,7 +257,11 @@ static inline void protected_flush_icach */ static inline void protected_writeback_dcache_line(unsigned long addr) { +#ifdef CONFIG_EVA + protected_cachee_op(Hit_Writeback_Inv_D, addr); +#else protected_cache_op(Hit_Writeback_Inv_D, addr); +#endif } static inline void protected_writeback_scache_line(unsigned long addr)