From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: deepak.s@linux.intel.com
Cc: daniel.vetter@ffwll.ch, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Forcewake Register Range changes for CHV
Date: Wed, 10 Dec 2014 16:31:54 +0200 [thread overview]
Message-ID: <20141210143154.GA10649@intel.com> (raw)
In-Reply-To: <1418282321-8525-1-git-send-email-deepak.s@linux.intel.com>
On Thu, Dec 11, 2014 at 12:48:41PM +0530, deepak.s@linux.intel.com wrote:
> From: Deepak S <deepak.s@linux.intel.com>
>
> According to updated BSpec, Render/Common Wells register range changed.
> Updating the same to match the spec and avoid extra forcewake for none
> forcewake range.
>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 9 +++------
> 1 file changed, 3 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 46de8d7..dd36f9b 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -647,9 +647,9 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
>
> #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
> (REG_RANGE((reg), 0x2000, 0x4000) || \
> - REG_RANGE((reg), 0x5000, 0x8000) || \
> + REG_RANGE((reg), 0x5200, 0x8000) || \
> REG_RANGE((reg), 0x8300, 0x8500) || \
> - REG_RANGE((reg), 0xB000, 0xC000) || \
> + REG_RANGE((reg), 0xB000, 0xB480) || \
> REG_RANGE((reg), 0xE000, 0xE800))
>
> #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
> @@ -665,10 +665,7 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
> REG_RANGE((reg), 0x8000, 0x8300) || \
> REG_RANGE((reg), 0x8500, 0x8600) || \
> REG_RANGE((reg), 0x9000, 0xB000) || \
> - REG_RANGE((reg), 0xC000, 0xC800) || \
> - REG_RANGE((reg), 0xF000, 0x10000) || \
> - REG_RANGE((reg), 0x14000, 0x14400) || \
> - REG_RANGE((reg), 0x22000, 0x24000))
> + REG_RANGE((reg), 0xF000, 0x10000))
Looks correct.
It looks like the media offsets could use a small adjustment as well:
- REG_RANGE((reg), 0x30000, 0x40000)
+ REG_RANGE((reg), 0x30000, 0x38000)
So with that changed
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
One thing I don't understand though; Why is the [0x100000,0x180000[ range
marked as GWK in the spreadsheet? That's where the forcewake req/ack
registers live as well as some other GTFIFO stuff etc. How can you take
forcewake if the forcewake req/ack itself would need forcewake. I think
this must be an error in the spreadsheet and that range should be GNW.
>
> #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
> REG_RANGE((reg), 0xB00, 0x2000)
> --
> 1.9.1
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2014-12-10 14:32 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-11 7:18 [PATCH] drm/i915: Forcewake Register Range changes for CHV deepak.s
2014-12-10 14:31 ` Ville Syrjälä [this message]
2014-12-11 16:04 ` Deepak S
2014-12-11 16:12 ` [PATCH v2] " deepak.s
2014-12-10 17:02 ` Daniel Vetter
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