From: thomas.petazzoni@free-electrons.com (Thomas Petazzoni)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 1/1] net/macb: add TX multiqueue support for gem
Date: Thu, 11 Dec 2014 20:31:03 +0100 [thread overview]
Message-ID: <20141211203103.4191887a@free-electrons.com> (raw)
In-Reply-To: <87a3098203ee6eaa7a60607713a293d3258e2b58.1418291637.git.cyrille.pitchen@atmel.com>
Dear Cyrille Pitchen,
On Thu, 11 Dec 2014 11:16:51 +0100, Cyrille Pitchen wrote:
> +#define GEM_ISR1 0x0400
> +#define GEM_ISR2 0x0404
> +#define GEM_ISR3 0x0408
> +#define GEM_ISR4 0x040c
> +#define GEM_ISR5 0x0410
> +#define GEM_ISR6 0x0414
> +#define GEM_ISR7 0x0418
What about doing instead:
#define GEM_ISR(q) ((q) == 0 ? MACB_ISR : 0x400 + (q) << 2)
And ditto for all other registers, which will save a lot of boring repeated code.
If you do that, then you can avoid the following fields in the
macb_queue structure:
+ unsigned int ISR;
+ unsigned int IER;
+ unsigned int IDR;
+ unsigned int IMR;
+ unsigned int TBQP;
And the not very pleasant calculation of those offsets:
+ bp->queues[0].bp = bp;
+ bp->queues[0].ISR = MACB_ISR;
+ bp->queues[0].IER = MACB_IER;
+ bp->queues[0].IDR = MACB_IDR;
+ bp->queues[0].IMR = MACB_IMR;
+ bp->queues[0].TBQP = MACB_TBQP;
+ for (q = 1, queue = &bp->queues[1]; q < MACB_MAX_QUEUES; ++q) {
+ if (!(queue_mask & (1 << q)))
+ continue;
+
+ queue->bp = bp;
+ queue->ISR = (q-1) * sizeof(u32) + GEM_ISR1;
+ queue->IER = (q-1) * sizeof(u32) + GEM_IER1;
+ queue->IDR = (q-1) * sizeof(u32) + GEM_IDR1;
+ queue->IMR = (q-1) * sizeof(u32) + GEM_IMR1;
+ queue->TBQP = (q-1) * sizeof(u32) + GEM_TBQP1;
+ queue++;
+ }
You replace the ISR, IER, IDR, IMR and TBQP by an "id" field in
macb_queue, which contains the queue number, and then change your:
+#define queue_readl(queue, reg) \
+ __raw_readl((queue)->bp->regs + queue->reg)
+#define queue_writel(queue, reg, value) \
+ __raw_writel((value), (queue)->bp->regs + queue->reg)
to
+#define queue_readl(queue, reg) \
+ __raw_readl((queue)->bp->regs + reg((queue)->id))
+#define queue_writel(queue, reg, value) \
+ __raw_writel((value), (queue)->bp->regs + reg((queue)->id)
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
WARNING: multiple messages have this Message-ID (diff)
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
To: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Cc: <nicolas.ferre@atmel.com>, <davem@davemloft.net>,
<linux-arm-kernel@lists.infradead.org>, <netdev@vger.kernel.org>,
<soren.brinkmann@xilinx.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/1] net/macb: add TX multiqueue support for gem
Date: Thu, 11 Dec 2014 20:31:03 +0100 [thread overview]
Message-ID: <20141211203103.4191887a@free-electrons.com> (raw)
In-Reply-To: <87a3098203ee6eaa7a60607713a293d3258e2b58.1418291637.git.cyrille.pitchen@atmel.com>
Dear Cyrille Pitchen,
On Thu, 11 Dec 2014 11:16:51 +0100, Cyrille Pitchen wrote:
> +#define GEM_ISR1 0x0400
> +#define GEM_ISR2 0x0404
> +#define GEM_ISR3 0x0408
> +#define GEM_ISR4 0x040c
> +#define GEM_ISR5 0x0410
> +#define GEM_ISR6 0x0414
> +#define GEM_ISR7 0x0418
What about doing instead:
#define GEM_ISR(q) ((q) == 0 ? MACB_ISR : 0x400 + (q) << 2)
And ditto for all other registers, which will save a lot of boring repeated code.
If you do that, then you can avoid the following fields in the
macb_queue structure:
+ unsigned int ISR;
+ unsigned int IER;
+ unsigned int IDR;
+ unsigned int IMR;
+ unsigned int TBQP;
And the not very pleasant calculation of those offsets:
+ bp->queues[0].bp = bp;
+ bp->queues[0].ISR = MACB_ISR;
+ bp->queues[0].IER = MACB_IER;
+ bp->queues[0].IDR = MACB_IDR;
+ bp->queues[0].IMR = MACB_IMR;
+ bp->queues[0].TBQP = MACB_TBQP;
+ for (q = 1, queue = &bp->queues[1]; q < MACB_MAX_QUEUES; ++q) {
+ if (!(queue_mask & (1 << q)))
+ continue;
+
+ queue->bp = bp;
+ queue->ISR = (q-1) * sizeof(u32) + GEM_ISR1;
+ queue->IER = (q-1) * sizeof(u32) + GEM_IER1;
+ queue->IDR = (q-1) * sizeof(u32) + GEM_IDR1;
+ queue->IMR = (q-1) * sizeof(u32) + GEM_IMR1;
+ queue->TBQP = (q-1) * sizeof(u32) + GEM_TBQP1;
+ queue++;
+ }
You replace the ISR, IER, IDR, IMR and TBQP by an "id" field in
macb_queue, which contains the queue number, and then change your:
+#define queue_readl(queue, reg) \
+ __raw_readl((queue)->bp->regs + queue->reg)
+#define queue_writel(queue, reg, value) \
+ __raw_writel((value), (queue)->bp->regs + queue->reg)
to
+#define queue_readl(queue, reg) \
+ __raw_readl((queue)->bp->regs + reg((queue)->id))
+#define queue_writel(queue, reg, value) \
+ __raw_writel((value), (queue)->bp->regs + reg((queue)->id)
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
next prev parent reply other threads:[~2014-12-11 19:31 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-11 10:16 [PATCH v2 0/1] net/macb: add TX multiqueue support for gem Cyrille Pitchen
2014-12-11 10:16 ` Cyrille Pitchen
2014-12-11 10:16 ` [PATCH v2 1/1] " Cyrille Pitchen
2014-12-11 10:16 ` Cyrille Pitchen
2014-12-11 19:31 ` Thomas Petazzoni [this message]
2014-12-11 19:31 ` Thomas Petazzoni
2014-12-12 8:24 ` Cyrille Pitchen
2014-12-12 8:24 ` Cyrille Pitchen
2014-12-12 9:45 ` David Laight
2014-12-12 9:45 ` David Laight
2014-12-12 8:59 ` Cyrille Pitchen
2014-12-12 8:59 ` Cyrille Pitchen
2014-12-12 9:59 ` David Laight
2014-12-12 9:59 ` David Laight
2014-12-12 9:57 ` Cyrille Pitchen
2014-12-12 9:57 ` Cyrille Pitchen
2014-12-12 9:52 ` Thomas Petazzoni
2014-12-12 9:52 ` Thomas Petazzoni
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