Re: [PATCH v2] drm/i915: Use true PPGTT in Gen8+ when execlists are enabled

[Daniel Vetter <daniel@ffwll.ch>]

On Mon, Dec 15, 2014 at 04:08:37PM +0100, Daniel Vetter wrote:
> On Mon, Dec 15, 2014 at 02:58:00PM +0000, Michel Thierry wrote:
> > In Gen8+, full ppgtt needs execlist, otherwise the ctx switch can hang.
> > 
> > Also remove the current restriction, a user should be able to explicitly set
> > ppgtt=2.
> > 
> > Note, this patch considers that execlist support has been enabled by
> > default on Gen8.
> > 
> > v2: Remove non-default restriction and clarify comment (Daniel)
> 
> Missing git add since there's no no comment any more?

Ok, Michel clarified on irc that he meant commit message. I've fixed that
up and merged the patch.
-Daniel

> -Daniel
> 
> > 
> > Cc: Daniel Vetter <daniel@ffwll.ch>
> > Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ++++---
> >  1 file changed, 4 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index 171f6ea..b64323b 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -40,8 +40,6 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
> >  
> >  	has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
> >  	has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
> > -	if (IS_GEN8(dev))
> > -		has_full_ppgtt = false; /* XXX why? */
> >  
> >  	/*
> >  	 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
> > @@ -72,7 +70,10 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
> >  		return 0;
> >  	}
> >  
> > -	return has_aliasing_ppgtt ? 1 : 0;
> > +	if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
> > +		return 2;
> > +	else
> > +		return has_aliasing_ppgtt ? 1 : 0;
> >  }
> >  
> >  
> > -- 
> > 2.1.1
> > 
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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