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Date:   Thu, 18 Dec 2014 20:01:25 +0100
From:   Ralf Baechle <ralf@linux-mips.org>
To:     David Daney <ddaney.cavm@gmail.com>
Cc:     Markos Chandras <markos.chandras@imgtec.com>,
        linux-mips@linux-mips.org,
        Matthew Fortune <Matthew.Fortune@imgtec.com>
Subject: Re: [PATCH RFC 19/67] MIPS: asm: atomic: Update asm and ISA
 constrains for MIPS R6 support
Message-ID: <20141218190125.GA8221@linux-mips.org>
References: <1418915416-3196-1-git-send-email-markos.chandras@imgtec.com>
 <1418915416-3196-20-git-send-email-markos.chandras@imgtec.com>
 <549321F3.1090704@gmail.com>
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On Thu, Dec 18, 2014 at 10:50:27AM -0800, David Daney wrote:

> On 12/18/2014 07:09 AM, Markos Chandras wrote:
> >MIPS R6 changed the opcodes for LL/SC instructions and reduced the
> >offset field to 9-bits. This has some undesired effects with the "m"
> >constrain since it implies a 16-bit immediate. As a result of which,
> >add a register ("r") constrain as well to make sure the entire address
> >is loaded to a register before the LL/SC operations. Also use macro
> >to set the appropriate ISA for the asm blocks
> >
> 
> Has support for MIPS R6 been added to GCC?
> 
> If so, that should include a proper constraint to be used with the new
> offset restrictions.  We should probably use that, instead of forcing to a
> "r" constraint.

In a non-public earlier discussion I've requested the same but somehow
that was ignored.

We need suitable constraints or the alternatives will be very, very ugly.

  Ralf