[PATCH v2 3/4] mmc: sunxi: Convert MMC driver to the standard clock phase API

[maxime.ripard@free-electrons.com (Maxime Ripard)]

On Wed, Dec 17, 2014 at 12:17:36PM +0800, Chen-Yu Tsai wrote:
> >         /* determine delays */
> >         if (rate <= 400000) {
> > -               oclk_dly = 0;
> > -               sclk_dly = 7;
> > +               oclk_dly = 180;
> > +               sclk_dly = 42;
> 
> 42 seems like an odd number. Maybe 45?

If the rate is at 400kHz, that means that the clock in muxed from the
24M, with a divider of 60.

That means that we can outphase the clocks only by a multiple of 6
(360 / 60). 7 * 6 = 42.

Depending on how the rounding goes, 45 might work too, but if we wan't
to be conservative, 42 doesn't change anything, 45 does.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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