From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vince Hsu Subject: Re: [PATCH 3/11] memory: tegra: add flush operation for Tegra124 memory clients Date: Tue, 6 Jan 2015 23:53:13 +0800 Message-ID: <20150106155312.GA20547@nvidia.com> References: <1419331204-26679-1-git-send-email-vinceh@nvidia.com> <1419331204-26679-4-git-send-email-vinceh@nvidia.com> <20150106142958.GM31830@ulmo.nvidia.com> <20150106150744.GB18598@nvidia.com> <20150106152750.GR31830@ulmo.nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20150106152750.GR31830-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org> Content-Disposition: inline List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: nouveau-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Nouveau" To: Thierry Reding Cc: swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org, nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, bskeggs-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, seven-FA6nBp6kBxZzu6KWmfFNGwC/G2K4zDHf@public.gmane.org List-Id: linux-tegra@vger.kernel.org T24gMDQ6Mjc6NTJQTSBKYW4gMDYsIFRoaWVycnkgUmVkaW5nIHdyb3RlOgo+ICogUEdQIFNpZ25l ZCBieSBhbiB1bmtub3duIGtleQo+IAo+IE9uIFR1ZSwgSmFuIDA2LCAyMDE1IGF0IDExOjA3OjQ1 UE0gKzA4MDAsIFZpbmNlIEhzdSB3cm90ZToKPiA+IE9uIDAzOjMwOjAwUE0gSmFuIDA2LCBUaGll cnJ5IFJlZGluZyB3cm90ZToKPiA+ID4gPiBPbGQgU2lnbmVkIGJ5IGFuIHVua25vd24ga2V5Cj4g PiA+IAo+ID4gPiBPbiBUdWUsIERlYyAyMywgMjAxNCBhdCAwNjozOTo1NlBNICswODAwLCBWaW5j ZSBIc3Ugd3JvdGU6Cj4gPiA+ID4gU2lnbmVkLW9mZi1ieTogVmluY2UgSHN1IDx2aW5jZWhAbnZp ZGlhLmNvbT4KPiA+ID4gPiAtLS0KPiA+ID4gPiAgZHJpdmVycy9tZW1vcnkvdGVncmEvdGVncmEx MjQuYyB8IDgyICsrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrCj4gPiA+ ID4gIDEgZmlsZSBjaGFuZ2VkLCA4MiBpbnNlcnRpb25zKCspCj4gPiA+ID4gCj4gPiA+ID4gZGlm ZiAtLWdpdCBhL2RyaXZlcnMvbWVtb3J5L3RlZ3JhL3RlZ3JhMTI0LmMgYi9kcml2ZXJzL21lbW9y eS90ZWdyYS90ZWdyYTEyNC5jCj4gPiA+ID4gaW5kZXggMjc4ZDQwYjg1NGMxLi4wMzY5MzU3NDNh MGEgMTAwNjQ0Cj4gPiA+ID4gLS0tIGEvZHJpdmVycy9tZW1vcnkvdGVncmEvdGVncmExMjQuYwo+ ID4gPiA+ICsrKyBiL2RyaXZlcnMvbWVtb3J5L3RlZ3JhL3RlZ3JhMTI0LmMKPiA+ID4gPiBAQCAt Niw2ICs2LDcgQEAKPiA+ID4gPiAgICogcHVibGlzaGVkIGJ5IHRoZSBGcmVlIFNvZnR3YXJlIEZv dW5kYXRpb24uCj4gPiA+ID4gICAqLwo+ID4gPiA+ICAKPiA+ID4gPiArI2luY2x1ZGUgPGxpbnV4 L2RlbGF5Lmg+Cj4gPiA+ID4gICNpbmNsdWRlIDxsaW51eC9vZi5oPgo+ID4gPiA+ICAjaW5jbHVk ZSA8bGludXgvbW0uaD4KPiA+ID4gPiAgCj4gPiA+ID4gQEAgLTk1OSw3ICs5NjAsODUgQEAgc3Rh dGljIGNvbnN0IHN0cnVjdCB0ZWdyYV9zbW11X3N3Z3JvdXAgdGVncmExMjRfc3dncm91cHNbXSA9 IHsKPiA+ID4gPiAgCXsgLnN3Z3JvdXAgPSBURUdSQV9TV0dST1VQX1ZJLCAgICAgICAgLnJlZyA9 IDB4MjgwIH0sCj4gPiA+ID4gIH07Cj4gPiA+ID4gIAo+ID4gPiA+ICtzdGF0aWMgY29uc3Qgc3Ry dWN0IHRlZ3JhX21jX2hyIHRlZ3JhMTI0X21jX2hyW10gPSB7Cj4gPiA+ID4gKwl7VEVHUkFfU1dH Uk9VUF9BRkksICAgICAgICAweDIwMCwgMHgyMDAsICAwfSwKPiA+ID4gPiArCXtURUdSQV9TV0dS T1VQX0FWUEMsICAgICAgIDB4MjAwLCAweDIwMCwgIDF9LAo+ID4gPiA+ICsJe1RFR1JBX1NXR1JP VVBfREMsICAgICAgICAgMHgyMDAsIDB4MjAwLCAgMn0sCj4gPiA+ID4gKwl7VEVHUkFfU1dHUk9V UF9EQ0IsICAgICAgICAweDIwMCwgMHgyMDAsICAzfSwKPiA+ID4gPiArCXtURUdSQV9TV0dST1VQ X0hDLCAgICAgICAgIDB4MjAwLCAweDIwMCwgIDZ9LAo+ID4gPiA+ICsJe1RFR1JBX1NXR1JPVVBf SERBLCAgICAgICAgMHgyMDAsIDB4MjAwLCAgN30sCj4gPiA+ID4gKwl7VEVHUkFfU1dHUk9VUF9J U1AyLCAgICAgICAweDIwMCwgMHgyMDAsICA4fSwKPiA+ID4gPiArCXtURUdSQV9TV0dST1VQX01Q Q09SRSwgICAgIDB4MjAwLCAweDIwMCwgIDl9LAo+ID4gPiA+ICsJe1RFR1JBX1NXR1JPVVBfTVBD T1JFTFAsICAgMHgyMDAsIDB4MjAwLCAxMH0sCj4gPiA+ID4gKwl7VEVHUkFfU1dHUk9VUF9NU0VO QywgICAgICAweDIwMCwgMHgyMDAsIDExfSwKPiA+ID4gPiArCXtURUdSQV9TV0dST1VQX1BQQ1Ms ICAgICAgIDB4MjAwLCAweDIwMCwgMTR9LAo+ID4gPiA+ICsJe1RFR1JBX1NXR1JPVVBfU0FUQSwg ICAgICAgMHgyMDAsIDB4MjAwLCAxNX0sCj4gPiA+ID4gKwl7VEVHUkFfU1dHUk9VUF9WREUsICAg ICAgICAweDIwMCwgMHgyMDAsIDE2fSwKPiA+ID4gPiArCXtURUdSQV9TV0dST1VQX1ZJLCAgICAg ICAgIDB4MjAwLCAweDIwMCwgMTd9LAo+ID4gPiA+ICsJe1RFR1JBX1NXR1JPVVBfVklDLCAgICAg ICAgMHgyMDAsIDB4MjAwLCAxOH0sCj4gPiA+ID4gKwl7VEVHUkFfU1dHUk9VUF9YVVNCX0hPU1Qs ICAweDIwMCwgMHgyMDAsIDE5fSwKPiA+ID4gPiArCXtURUdSQV9TV0dST1VQX1hVU0JfREVWLCAg IDB4MjAwLCAweDIwMCwgMjB9LAo+ID4gPiA+ICsJe1RFR1JBX1NXR1JPVVBfVFNFQywgICAgICAg MHgyMDAsIDB4MjAwLCAyMn0sCj4gPiA+ID4gKwl7VEVHUkFfU1dHUk9VUF9TRE1NQzFBLCAgICAw eDIwMCwgMHgyMDAsIDI5fSwKPiA+ID4gPiArCXtURUdSQV9TV0dST1VQX1NETU1DMkEsICAgIDB4 MjAwLCAweDIwMCwgMzB9LAo+ID4gPiA+ICsJe1RFR1JBX1NXR1JPVVBfU0RNTUMzQSwgICAgMHgy MDAsIDB4MjAwLCAzMX0sCj4gPiA+IAo+ID4gPiBUaGUgZG9jdW1lbnRhdGlvbiB0aGF0IEkgaGF2 ZSBzYXlzIHRoYXQgdGhlIHN0YXR1cyByZWdpc3RlciBmb3IgdGhlc2UgaXMKPiA+ID4gMHgyMDQu Cj4gPiBPb3BzLiBUaGFua3MgZm9yIGNhdGNoaW5nIHRoaXMuIFdpbGwgZml4Lgo+ID4gCj4gPiA+ IAo+ID4gPiA+ICsJe1RFR1JBX1NXR1JPVVBfU0RNTUM0QSwgICAgMHg5NzAsIDB4OTc0LCAgMH0s Cj4gPiA+ID4gKwl7VEVHUkFfU1dHUk9VUF9JU1AyQiwgICAgICAweDk3MCwgMHg5NzQsICAxfSwK PiA+ID4gPiArCXtURUdSQV9TV0dST1VQX0dQVSwgICAgICAgIDB4OTcwLCAweDk3NCwgIDJ9LAo+ ID4gPiA+ICt9Owo+ID4gPiA+ICsKPiA+ID4gPiAgI2lmZGVmIENPTkZJR19BUkNIX1RFR1JBXzEy NF9TT0MKPiA+ID4gPiArCj4gPiA+ID4gK3N0YXRpYyBib29sIHRlZ3JhMTI0X3N0YWJsZV9ob3Ry ZXNldF9jaGVjayhzdHJ1Y3QgdGVncmFfbWMgKm1jLAo+ID4gPiA+ICsJCXUzMiByZWcsIHUzMiAq c3RhdCkKPiA+ID4gPiArewo+ID4gPiA+ICsJaW50IGk7Cj4gPiA+ID4gKwl1MzIgY3VyX3N0YXQ7 Cj4gPiA+ID4gKwl1MzIgcHJ2X3N0YXQ7Cj4gPiA+ID4gKwo+ID4gPiA+ICsJcHJ2X3N0YXQgPSBt Y19yZWFkbChtYywgcmVnKTsKPiA+ID4gPiArCWZvciAoaSA9IDA7IGkgPCA1OyBpKyspIHsKPiA+ ID4gPiArCQljdXJfc3RhdCA9IG1jX3JlYWRsKG1jLCByZWcpOwo+ID4gPiA+ICsJCWlmIChjdXJf c3RhdCAhPSBwcnZfc3RhdCkKPiA+ID4gPiArCQkJcmV0dXJuIGZhbHNlOwo+ID4gPiA+ICsJfQo+ ID4gPiAKPiA+ID4gV2h5IHRoaXMgbG9vcD8gVGhlIGZ1bmN0aW9uIGlzIGFscmVhZHkgY2FsbGVk IGluIGEgcG9sbGluZyBsb29wIGJlbG93Lgo+ID4gPiBBbHNvIHdoeSBjb21wYXJlIHRvIHRoZSBw cmV2aW91cyB2YWx1ZSBvZiB0aGUgcmVnaXN0ZXI/IElzbid0IHRoZSBvbmx5Cj4gPiA+IHRoaW5n IHdlJ3JlIGludGVyZXN0ZWQgaW4gdGhlIHZhbHVlIG9mIHRoZSBzcGVjaWZpYyBiaXQ/Cj4gPiBJ IHJlY2FsbCBpdCdzIGR1ZSB0byBhIEhXIGJ1ZyB0aGF0IHRoZXJlIG1pZ2h0IGJlIGEgZ2l0Y2gg aWYgd2UgcHJvZ3JhbQo+ID4gdGhlIGN0cmwgcmVnIGFuZCB0aGVuIHJlYWQgdGhlIHN0YXR1cyBy ZWcgaW4gYSBzaG9ydCB3aW5kb3cuIFRoaXMgZnVuY3Rpb24KPiA+IGlzIHRvIG1ha2Ugc3VyZSB3 ZSBoYXZlIGEgc3RhYmxlIHN0YXR1cy4KPiAKPiBUaGlzIHdhcnJhbnRzIGEgY29tbWVudCwgdGhl bi4KT2theS4KCj4gCj4gPiA+ID4gKwkqc3RhdCA9IGN1cl9zdGF0Owo+ID4gPiA+ICsJcmV0dXJu IHRydWU7Cj4gPiA+ID4gK30KPiA+ID4gPiArCj4gPiA+ID4gK3N0YXRpYyBpbnQgdGVncmExMjRf bWNfZmx1c2goc3RydWN0IHRlZ3JhX21jICptYywKPiA+ID4gPiArCQljb25zdCBzdHJ1Y3QgdGVn cmFfbWNfaHIgKmhyX2NsaWVudCwgYm9vbCBlbmFibGUpCj4gPiA+ID4gK3sKPiA+ID4gPiArCXUz MiB2YWw7Cj4gPiA+ID4gKwo+ID4gPiA+ICsJaWYgKCFtYyB8fCAhaHJfY2xpZW50KQo+ID4gPiA+ ICsJCXJldHVybiAtRUlOVkFMOwo+ID4gPiA+ICsKPiA+ID4gPiArCXZhbCA9IG1jX3JlYWRsKG1j LCBocl9jbGllbnQtPmN0cmwpOwo+ID4gPiA+ICsJaWYgKGVuYWJsZSkKPiA+ID4gPiArCQl2YWwg fD0gQklUKGhyX2NsaWVudC0+Yml0KTsKPiA+ID4gPiArCWVsc2UKPiA+ID4gPiArCQl2YWwgJj0g fkJJVChocl9jbGllbnQtPmJpdCk7Cj4gPiA+ID4gKwltY193cml0ZWwobWMsIHZhbCwgaHJfY2xp ZW50LT5jdHJsKTsKPiA+ID4gPiArCW1jX3JlYWRsKG1jLCBocl9jbGllbnQtPmN0cmwpOwo+ID4g PiA+ICsKPiA+ID4gPiArCS8qIHBvbGwgdGlsbCB0aGUgZmx1c2ggaXMgZG9uZSAqLwo+ID4gPiA+ ICsJaWYgKGVuYWJsZSkgewo+ID4gPiA+ICsJCWRvIHsKPiA+ID4gPiArCQkJdWRlbGF5KDEwKTsK PiA+ID4gCj4gPiA+IFRoaXMgc2hvdWxkIHByb2JhYmx5IGJlIHVzbGVlcF9yYW5nZSgxMCwgMjAp IG9yIHNvbWV0aGluZy4KPiA+IE1heWJlIG5vLiBXZSBtaWdodCBuZWVkIHNvbWUgc3BpbiBsb2Nr IGhlcmUgdG8gZW5zdXJlIG9ubHkgb25lIGZsdXNoaW5nCj4gPiBvcGVyYXRpb24gcmVxdWVzdGVk IGFuZCBubyByYWNlIGNvdWxkIGhhcHBlbi4KPiAKPiBXZSBzaG91bGQgdXNlIGEgbXV0ZXgsIHRo ZW4uIFRoZXJlJ3Mgbm8gc2F5aW5nIGhvdyBsb25nIHRoaXMgd2lsbCB0YWtlCj4gYW5kIGJ1c3kt bG9vcGluZyBpbmRlZmluaXRlbHkgaXMgYSBiYWQgaWRlYS4gVGhvdWdoIGl0IHNlZW1zIHRvIG1l IGxpa2UKPiB3ZSBkb24ndCBuZWVkIHRvIGxvY2sgYXJvdW5kIHRoZSBwb2xsaW5nIGxvb3AgaGVy ZSBzaW5jZSB3ZSdyZSBtZXJlbHkKPiByZWFkaW5nIGEgc3RhdHVzIHJlZ2lzdGVyLiBXZSB3b3Vs ZCBvbmx5IG5lZWQgdG8gbG9jayBhcm91bmQgYWNjZXNzZXMgdG8KPiB0aGUgY29udHJvbCByZWdp c3RlciB0byBtYWtlIHN1cmUgdHdvIHByb2Nlc3NlcyBjYW4ndCBzdGVwIG9uIGVhY2gKPiBvdGhl cnMncyB0b2VzLgpXZSBjYW4gdXNlIG1ldHV4IGRlZmluaXRlbHkuIElmIHR3byBwcm9jZXNzZXMg dG91Y2ggdGhlIGN0cmwgcmVnaXN0ZXJzCnNlcXVlbnRpYWxseSBhbmQgcG9sbCB0aGUgc3RhdHVz IHJlZ2lzdGVyIGluIHBhcmFsbGVsLCB3ZSBkb250JyBrbm93IHdoZXRoZXIKdGhlIGdsaXRjaCBp cyBjYXVzZWQgYnkgdGhlIEhXIGJ1ZyBvciB0aGUgY29uY3VycmVudCBjdHJsIHJlZ2lzdGVyIHBy b2dyYW1taW5nPwpXZSBzaG91bGQgbG9jayB0aGUgc3RhdHVzIGNoZWNraW5nIGFzIHdlbGwuCgo+ IAo+ID4gPiBXb3VsZCBpdCBiZSBkaWZmaWN1bHQgdG8gaW1wbGVtZW50IHRoaXMgZm9yIFRlZ3Jh MzAgYW5kIFRlZ3JhMTE0Pwo+ID4gTm8uIEJ1dCBJIGhhdmUgdG8gY2hlY2sgdGhlIGRldGFpbCBp biBUZWdyYTMwIGFuZCBUZWdyYTExNC4gQW5kIHRoZSBiaWdnZXN0Cj4gPiBwcm9ibGVtIGlzIEkg ZG9uJ3QgaGF2ZSB0aGUgYm9hcmRzIHRvIHRlc3QuCj4gCj4gSSBjYW4gaGVscCB3aXRoIHRlc3Rp bmcuIFRob3VnaCB0aGF0IHJhaXNlcyB0aGUgcXVlc3Rpb24gb2YgaG93IHRoaXMgY2FuCj4gYmUg dGVzdGVkLiBJdCBzZWVtcyBsaWtlIHRoaXMgZmVhdHVyZSBpcyB1c2VkIHRvIG1ha2Ugc3VyZSB0 aGF0IGFsbAo+IG91dHN0YW5kaW5nIG1lbW9yeSByZXF1ZXN0cyBmcm9tIGNsaWVudHMgYXJlIGZs dXNoZWQgYmVmb3JlIHJlc2V0dGluZyBhCj4gbW9kdWxlLiBUeXBpY2FsbHkgTGludXggYXNzdW1l cyB0aGF0IGRldmljZXMgZG8gdGhhdCBhbnl3YXksIHNvIGlmIGEKPiBkZXZpY2UgaXMgc3VzcGVu ZGVkIG9yIHNodXQgZG93biwgdGhlIGNvcnJlc3BvbmRpbmcgZnVuY3Rpb24gc2hvdWxkCj4gZW5z dXJlIHRoYXQgYWxsIG91dHN0YW5kaW5nIHRyYW5zZmVycyBoYXZlIGJlZW4gY2FuY2VsbGVkIGFu ZCBhcmUKPiBmbHVzaGVkLgpUaGUgZmx1c2hpbmcgb3BlcmF0aW9uIGNhbiBiZSByZXF1ZXN0ZWQg YnkgcnVudGltZSBQTSBpZiB0aGUgZGV2aWNlIHN1cHBvcnRzCml0LgoKPiAKPiBBbHNvIHdlJ3Zl IG1hbmFnZWQganVzdCBmaW5lIHNvIGZhciwgc28gSSdtIGJlZ2lubmluZyB0byB3b25kZXIgd2hl dGhlcgo+IHdlIGFjdHVhbGx5IG5lZWQgdGhpcyBmZWF0dXJlIG9uIExpbnV4LiBJZiBub3QsIGhv dyBkbyB3ZSB0ZXN0IHRoYXQgdGhpcwo+IGlzIGluZGVlZCBkb2luZyB3aGF0IGl0IHNob3VsZD8g SG93IHRvIHRyaWdnZXIgYSBjb25kaXRpb24gdGhhdCByZXF1aXJlcwo+IGZsdXNoaW5nIGFuZCBo b3cgZG8gd2UgZGV0ZXJtaW5lIHRoYXQgZmx1c2hpbmcgYWN0dWFsbHkgZml4ZXMgdGhpbmdzPwpT b3JyeSB0aGF0IEkgY2FuJ3QgYW5zd2VyIGhvdyB0byB0ZXN0IGl0IGJlY2F1c2UgSSdtIG5vdCBh IG1jIGV4cGVydC4KV2hhdCBJIGNhbiBkbyBpcyB0ZXN0aW5nIHRoZSBwb3dlciB1cC9vZmYgc2Vx dWVuY2UgYSBsb3Qgb2YgdGltZSBhbmQgY2hlY2sgaWYKdGhlIGRldmljZSBjYW4gc3RpbGwgd29y ayBub3JtYWxseS4gV2UgbmVlZCB0aGlzIGZlYXR1cmUgYmVjYXVzZSB0aGUgVFJNCnJlcXVpcmVz IHNvPwoKVGhhbmtzLApWaW5jZQoKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fCk5vdXZlYXUgbWFpbGluZyBsaXN0Ck5vdXZlYXVAbGlzdHMuZnJlZWRlc2t0 b3Aub3JnCmh0dHA6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9ub3V2 ZWF1Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756236AbbAFPxP (ORCPT ); Tue, 6 Jan 2015 10:53:15 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5593 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755733AbbAFPxN (ORCPT ); Tue, 6 Jan 2015 10:53:13 -0500 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 06 Jan 2015 07:46:02 -0800 Date: Tue, 6 Jan 2015 23:53:13 +0800 From: Vince Hsu To: Thierry Reding CC: , , , , , , , , Subject: Re: [PATCH 3/11] memory: tegra: add flush operation for Tegra124 memory clients Message-ID: <20150106155312.GA20547@nvidia.com> References: <1419331204-26679-1-git-send-email-vinceh@nvidia.com> <1419331204-26679-4-git-send-email-vinceh@nvidia.com> <20150106142958.GM31830@ulmo.nvidia.com> <20150106150744.GB18598@nvidia.com> <20150106152750.GR31830@ulmo.nvidia.com> MIME-Version: 1.0 In-Reply-To: <20150106152750.GR31830@ulmo.nvidia.com> User-Agent: Mutt/1.5.21 (2010-09-15) Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04:27:52PM Jan 06, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Tue, Jan 06, 2015 at 11:07:45PM +0800, Vince Hsu wrote: > > On 03:30:00PM Jan 06, Thierry Reding wrote: > > > > Old Signed by an unknown key > > > > > > On Tue, Dec 23, 2014 at 06:39:56PM +0800, Vince Hsu wrote: > > > > Signed-off-by: Vince Hsu > > > > --- > > > > drivers/memory/tegra/tegra124.c | 82 +++++++++++++++++++++++++++++++++++++++++ > > > > 1 file changed, 82 insertions(+) > > > > > > > > diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c > > > > index 278d40b854c1..036935743a0a 100644 > > > > --- a/drivers/memory/tegra/tegra124.c > > > > +++ b/drivers/memory/tegra/tegra124.c > > > > @@ -6,6 +6,7 @@ > > > > * published by the Free Software Foundation. > > > > */ > > > > > > > > +#include > > > > #include > > > > #include > > > > > > > > @@ -959,7 +960,85 @@ static const struct tegra_smmu_swgroup tegra124_swgroups[] = { > > > > { .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 }, > > > > }; > > > > > > > > +static const struct tegra_mc_hr tegra124_mc_hr[] = { > > > > + {TEGRA_SWGROUP_AFI, 0x200, 0x200, 0}, > > > > + {TEGRA_SWGROUP_AVPC, 0x200, 0x200, 1}, > > > > + {TEGRA_SWGROUP_DC, 0x200, 0x200, 2}, > > > > + {TEGRA_SWGROUP_DCB, 0x200, 0x200, 3}, > > > > + {TEGRA_SWGROUP_HC, 0x200, 0x200, 6}, > > > > + {TEGRA_SWGROUP_HDA, 0x200, 0x200, 7}, > > > > + {TEGRA_SWGROUP_ISP2, 0x200, 0x200, 8}, > > > > + {TEGRA_SWGROUP_MPCORE, 0x200, 0x200, 9}, > > > > + {TEGRA_SWGROUP_MPCORELP, 0x200, 0x200, 10}, > > > > + {TEGRA_SWGROUP_MSENC, 0x200, 0x200, 11}, > > > > + {TEGRA_SWGROUP_PPCS, 0x200, 0x200, 14}, > > > > + {TEGRA_SWGROUP_SATA, 0x200, 0x200, 15}, > > > > + {TEGRA_SWGROUP_VDE, 0x200, 0x200, 16}, > > > > + {TEGRA_SWGROUP_VI, 0x200, 0x200, 17}, > > > > + {TEGRA_SWGROUP_VIC, 0x200, 0x200, 18}, > > > > + {TEGRA_SWGROUP_XUSB_HOST, 0x200, 0x200, 19}, > > > > + {TEGRA_SWGROUP_XUSB_DEV, 0x200, 0x200, 20}, > > > > + {TEGRA_SWGROUP_TSEC, 0x200, 0x200, 22}, > > > > + {TEGRA_SWGROUP_SDMMC1A, 0x200, 0x200, 29}, > > > > + {TEGRA_SWGROUP_SDMMC2A, 0x200, 0x200, 30}, > > > > + {TEGRA_SWGROUP_SDMMC3A, 0x200, 0x200, 31}, > > > > > > The documentation that I have says that the status register for these is > > > 0x204. > > Oops. Thanks for catching this. Will fix. > > > > > > > > > + {TEGRA_SWGROUP_SDMMC4A, 0x970, 0x974, 0}, > > > > + {TEGRA_SWGROUP_ISP2B, 0x970, 0x974, 1}, > > > > + {TEGRA_SWGROUP_GPU, 0x970, 0x974, 2}, > > > > +}; > > > > + > > > > #ifdef CONFIG_ARCH_TEGRA_124_SOC > > > > + > > > > +static bool tegra124_stable_hotreset_check(struct tegra_mc *mc, > > > > + u32 reg, u32 *stat) > > > > +{ > > > > + int i; > > > > + u32 cur_stat; > > > > + u32 prv_stat; > > > > + > > > > + prv_stat = mc_readl(mc, reg); > > > > + for (i = 0; i < 5; i++) { > > > > + cur_stat = mc_readl(mc, reg); > > > > + if (cur_stat != prv_stat) > > > > + return false; > > > > + } > > > > > > Why this loop? The function is already called in a polling loop below. > > > Also why compare to the previous value of the register? Isn't the only > > > thing we're interested in the value of the specific bit? > > I recall it's due to a HW bug that there might be a gitch if we program > > the ctrl reg and then read the status reg in a short window. This function > > is to make sure we have a stable status. > > This warrants a comment, then. Okay. > > > > > + *stat = cur_stat; > > > > + return true; > > > > +} > > > > + > > > > +static int tegra124_mc_flush(struct tegra_mc *mc, > > > > + const struct tegra_mc_hr *hr_client, bool enable) > > > > +{ > > > > + u32 val; > > > > + > > > > + if (!mc || !hr_client) > > > > + return -EINVAL; > > > > + > > > > + val = mc_readl(mc, hr_client->ctrl); > > > > + if (enable) > > > > + val |= BIT(hr_client->bit); > > > > + else > > > > + val &= ~BIT(hr_client->bit); > > > > + mc_writel(mc, val, hr_client->ctrl); > > > > + mc_readl(mc, hr_client->ctrl); > > > > + > > > > + /* poll till the flush is done */ > > > > + if (enable) { > > > > + do { > > > > + udelay(10); > > > > > > This should probably be usleep_range(10, 20) or something. > > Maybe no. We might need some spin lock here to ensure only one flushing > > operation requested and no race could happen. > > We should use a mutex, then. There's no saying how long this will take > and busy-looping indefinitely is a bad idea. Though it seems to me like > we don't need to lock around the polling loop here since we're merely > reading a status register. We would only need to lock around accesses to > the control register to make sure two processes can't step on each > others's toes. We can use metux definitely. If two processes touch the ctrl registers sequentially and poll the status register in parallel, we dont' know whether the glitch is caused by the HW bug or the concurrent ctrl register programming? We should lock the status checking as well. > > > > Would it be difficult to implement this for Tegra30 and Tegra114? > > No. But I have to check the detail in Tegra30 and Tegra114. And the biggest > > problem is I don't have the boards to test. > > I can help with testing. Though that raises the question of how this can > be tested. It seems like this feature is used to make sure that all > outstanding memory requests from clients are flushed before resetting a > module. Typically Linux assumes that devices do that anyway, so if a > device is suspended or shut down, the corresponding function should > ensure that all outstanding transfers have been cancelled and are > flushed. The flushing operation can be requested by runtime PM if the device supports it. > > Also we've managed just fine so far, so I'm beginning to wonder whether > we actually need this feature on Linux. If not, how do we test that this > is indeed doing what it should? How to trigger a condition that requires > flushing and how do we determine that flushing actually fixes things? Sorry that I can't answer how to test it because I'm not a mc expert. What I can do is testing the power up/off sequence a lot of time and check if the device can still work normally. We need this feature because the TRM requires so? Thanks, Vince