From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-dev@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Improve HiZ throughput on Cherryview.
Date: Mon, 12 Jan 2015 15:00:02 +0200 [thread overview]
Message-ID: <20150112130002.GG10649@intel.com> (raw)
In-Reply-To: <1420941742-915-1-git-send-email-kenneth@whitecape.org>
On Sat, Jan 10, 2015 at 06:02:22PM -0800, Kenneth Graunke wrote:
> Found by reading the HIZ_CHICKEN documentation.
>
> Improves performance in a HiZ microbenchmark by around 50%.
> Improves performance in OglZBuffer by around 18%.
>
> Thanks to Chris Wilson for helping me figure out where to put this.
>
> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0f32fd1a..a39bb03 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5202,6 +5202,9 @@ enum punit_power_well {
> #define COMMON_SLICE_CHICKEN2 0x7014
> # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
>
> +#define HIZ_CHICKEN 0x7018
> +# define CHV_HZ_8X8_MODE_IN_1X (1<<15)
> +
> #define GEN7_L3SQCREG1 0xB010
> #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 12a36f0..dabc1d8 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -836,6 +836,9 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
> HDC_FORCE_NON_COHERENT |
> HDC_DONOT_FETCH_MEM_WHEN_MASKED);
>
> + /* Improve HiZ throughput on CHV. */
> + WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
> +
Nothing much in bspec about this bit. Can't see anything suspicious
in the w/a database either. So I guess we can assume it's safe.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
But I do wonder a bit if there's any relationship with the WIZ hashing
mode. Looks like we've not brought the 16x4 WIZ hashing mode change
over to CHV (or BYT for that matter), so I guess we're still using the
default 8x8 on these platforms. Might be interesting to see if there
are any gains to be had by changing it.
> return 0;
> }
>
> --
> 2.2.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
prev parent reply other threads:[~2015-01-12 13:00 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-11 2:02 [PATCH] drm/i915: Improve HiZ throughput on Cherryview Kenneth Graunke
2015-01-12 1:58 ` shuang.he
2015-01-12 13:00 ` Ville Syrjälä [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20150112130002.GG10649@intel.com \
--to=ville.syrjala@linux.intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=kenneth@whitecape.org \
--cc=mesa-dev@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.