From: Andrew Jones <drjones@redhat.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: Re: [Qemu-devel] [PATCH v2] tcg-arm: more instruction execution control
Date: Tue, 13 Jan 2015 16:46:45 +0100 [thread overview]
Message-ID: <20150113154644.GA19672@hawk.usersys.redhat.com> (raw)
In-Reply-To: <1421066807-4652-1-git-send-email-drjones@redhat.com>
On Mon, Jan 12, 2015 at 01:46:47PM +0100, Andrew Jones wrote:
> Cleanup XN/PXN handling in get_phys_addr_lpae, and implement all but
> EL2 support of the following ARMv8 sections
>
> D4.5.1 Memory access control: Access permissions for instruction
> execution
> G4.7.2 Execute-never restrictions on instruction fetching
>
> G4.7.2 matches the ARMv7 section B3.7.2 when long-descriptors are used.
>
> Signed-off-by: Andrew Jones <drjones@redhat.com>
>
While confirming the documentation wasn't wrong (it wasn't),
I see I missed another issue with qemu's instruction execution
control. For AArch64, EL0 can execute code even if it doesn't have
R/W access, i.e. AP[1]=0. To make this fix more clear I've done it
in a separate patch, and then rebased this patch on that. Thus,
please drop this patch, as I'll send a 2-patch patch series now
that replaces it.
drew
prev parent reply other threads:[~2015-01-13 15:46 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-09 17:06 [Qemu-devel] [PATCH] tcg-arm: more instruction execution control Andrew Jones
2015-01-12 12:42 ` Andrew Jones
2015-01-12 12:46 ` [Qemu-devel] [PATCH v2] " Andrew Jones
2015-01-13 15:46 ` Andrew Jones [this message]
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