diff for duplicates of <20150121164632.GK5044@leverpostej> diff --git a/a/1.txt b/N1/1.txt index eb8bad3..517b398 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -24,10 +24,10 @@ Mark. > This patch adds the L2 cache topology on Juno board, FVP/RTSM and > foundation models. > -> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> -> Cc: Mark Rutland <mark.rutland@arm.com> -> Cc: Liviu Dudau <Liviu.Dudau@arm.com> -> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> +> Signed-off-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org> +> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> +> Cc: Liviu Dudau <Liviu.Dudau-5wv7dgnIgG8@public.gmane.org> +> Cc: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> > --- > arch/arm64/boot/dts/arm/foundation-v8.dts | 8 ++++++++ > arch/arm64/boot/dts/arm/juno.dts | 14 ++++++++++++++ @@ -55,7 +55,7 @@ Mark. > cpu-release-addr = <0x0 0x8000fff8>; > + next-level-cache = <&L2_0>; > }; -> cpu at 1 { +> cpu@1 { > device_type = "cpu"; > @@ -41,6 +42,7 @@ > reg = <0x0 0x1>; @@ -63,7 +63,7 @@ Mark. > cpu-release-addr = <0x0 0x8000fff8>; > + next-level-cache = <&L2_0>; > }; -> cpu at 2 { +> cpu@2 { > device_type = "cpu"; > @@ -48,6 +50,7 @@ > reg = <0x0 0x2>; @@ -71,7 +71,7 @@ Mark. > cpu-release-addr = <0x0 0x8000fff8>; > + next-level-cache = <&L2_0>; > }; -> cpu at 3 { +> cpu@3 { > device_type = "cpu"; > @@ -55,6 +58,11 @@ > reg = <0x0 0x3>; @@ -96,7 +96,7 @@ Mark. > + next-level-cache = <&A57_L2>; > }; > -> A57_1: cpu at 1 { +> A57_1: cpu@1 { > @@ -46,6 +47,7 @@ > reg = <0x0 0x1>; > device_type = "cpu"; @@ -104,7 +104,7 @@ Mark. > + next-level-cache = <&A57_L2>; > }; > -> A53_0: cpu at 100 { +> A53_0: cpu@100 { > @@ -53,6 +55,7 @@ > reg = <0x0 0x100>; > device_type = "cpu"; @@ -112,7 +112,7 @@ Mark. > + next-level-cache = <&A53_L2>; > }; > -> A53_1: cpu at 101 { +> A53_1: cpu@101 { > @@ -60,6 +63,7 @@ > reg = <0x0 0x101>; > device_type = "cpu"; @@ -120,7 +120,7 @@ Mark. > + next-level-cache = <&A53_L2>; > }; > -> A53_2: cpu at 102 { +> A53_2: cpu@102 { > @@ -67,6 +71,7 @@ > reg = <0x0 0x102>; > device_type = "cpu"; @@ -128,7 +128,7 @@ Mark. > + next-level-cache = <&A53_L2>; > }; > -> A53_3: cpu at 103 { +> A53_3: cpu@103 { > @@ -74,6 +79,15 @@ > reg = <0x0 0x103>; > device_type = "cpu"; @@ -155,7 +155,7 @@ Mark. > cpu-release-addr = <0x0 0x8000fff8>; > + next-level-cache = <&L2_0>; > }; -> cpu at 1 { +> cpu@1 { > device_type = "cpu"; > @@ -44,6 +45,7 @@ > reg = <0x0 0x1>; @@ -163,7 +163,7 @@ Mark. > cpu-release-addr = <0x0 0x8000fff8>; > + next-level-cache = <&L2_0>; > }; -> cpu at 2 { +> cpu@2 { > device_type = "cpu"; > @@ -51,6 +53,7 @@ > reg = <0x0 0x2>; @@ -171,7 +171,7 @@ Mark. > cpu-release-addr = <0x0 0x8000fff8>; > + next-level-cache = <&L2_0>; > }; -> cpu at 3 { +> cpu@3 { > device_type = "cpu"; > @@ -58,6 +61,11 @@ > reg = <0x0 0x3>; @@ -188,4 +188,8 @@ Mark. > -- > 1.9.1 > -> +> +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 0d00d4f..693f962 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,8 +1,25 @@ "ref\01421841750-26722-1-git-send-email-sudeep.holla@arm.com\0" - "From\0mark.rutland@arm.com (Mark Rutland)\0" - "Subject\0[PATCH] arm64: Add L2 cache topology to ARM Ltd boards/models\0" + "ref\01421841750-26722-1-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org\0" + "From\0Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>\0" + "Subject\0Re: [PATCH] arm64: Add L2 cache topology to ARM Ltd boards/models\0" "Date\0Wed, 21 Jan 2015 16:46:32 +0000\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>\0" + "Cc\0linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>" + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + Lorenzo Pieralisi <Lorenzo.Pieralisi-5wv7dgnIgG8@public.gmane.org> + Catalin Marinas <Catalin.Marinas-5wv7dgnIgG8@public.gmane.org> + Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> + Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org> + Liviu Dudau <Liviu.Dudau-5wv7dgnIgG8@public.gmane.org> + Robert Richter <rrichter-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> + Radha Mohan Chintakuntla <rchintakuntla-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> + Kumar Sankaran <ksankaran-qTEPVZfXA3Y@public.gmane.org> + Loc Ho <lho-qTEPVZfXA3Y@public.gmane.org> + Feng Kan <fkan-qTEPVZfXA3Y@public.gmane.org> + Vinayak Kale <vkale-qTEPVZfXA3Y@public.gmane.org> + Suravee Suthikulpanit <Suravee.Suthikulpanit-5C7GfCeVMHo@public.gmane.org> + Thomas Lendacky <Thomas.Lendacky-5C7GfCeVMHo@public.gmane.org> + " Joel Schopp <Joel.Schopp-5C7GfCeVMHo@public.gmane.org>\0" "\00:1\0" "b\0" "On Wed, Jan 21, 2015 at 12:02:30PM +0000, Sudeep Holla wrote:\n" @@ -31,10 +48,10 @@ "> This patch adds the L2 cache topology on Juno board, FVP/RTSM and\n" "> foundation models.\n" "> \n" - "> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>\n" - "> Cc: Mark Rutland <mark.rutland@arm.com>\n" - "> Cc: Liviu Dudau <Liviu.Dudau@arm.com>\n" - "> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n" + "> Signed-off-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>\n" + "> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>\n" + "> Cc: Liviu Dudau <Liviu.Dudau-5wv7dgnIgG8@public.gmane.org>\n" + "> Cc: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>\n" "> ---\n" "> arch/arm64/boot/dts/arm/foundation-v8.dts | 8 ++++++++\n" "> arch/arm64/boot/dts/arm/juno.dts | 14 ++++++++++++++\n" @@ -62,7 +79,7 @@ "> \t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "> +\t\t\tnext-level-cache = <&L2_0>;\n" "> \t\t};\n" - "> \t\tcpu at 1 {\n" + "> \t\tcpu@1 {\n" "> \t\t\tdevice_type = \"cpu\";\n" "> @@ -41,6 +42,7 @@\n" "> \t\t\treg = <0x0 0x1>;\n" @@ -70,7 +87,7 @@ "> \t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "> +\t\t\tnext-level-cache = <&L2_0>;\n" "> \t\t};\n" - "> \t\tcpu at 2 {\n" + "> \t\tcpu@2 {\n" "> \t\t\tdevice_type = \"cpu\";\n" "> @@ -48,6 +50,7 @@\n" "> \t\t\treg = <0x0 0x2>;\n" @@ -78,7 +95,7 @@ "> \t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "> +\t\t\tnext-level-cache = <&L2_0>;\n" "> \t\t};\n" - "> \t\tcpu at 3 {\n" + "> \t\tcpu@3 {\n" "> \t\t\tdevice_type = \"cpu\";\n" "> @@ -55,6 +58,11 @@\n" "> \t\t\treg = <0x0 0x3>;\n" @@ -103,7 +120,7 @@ "> +\t\t\tnext-level-cache = <&A57_L2>;\n" "> \t\t};\n" "> \n" - "> \t\tA57_1: cpu at 1 {\n" + "> \t\tA57_1: cpu@1 {\n" "> @@ -46,6 +47,7 @@\n" "> \t\t\treg = <0x0 0x1>;\n" "> \t\t\tdevice_type = \"cpu\";\n" @@ -111,7 +128,7 @@ "> +\t\t\tnext-level-cache = <&A57_L2>;\n" "> \t\t};\n" "> \n" - "> \t\tA53_0: cpu at 100 {\n" + "> \t\tA53_0: cpu@100 {\n" "> @@ -53,6 +55,7 @@\n" "> \t\t\treg = <0x0 0x100>;\n" "> \t\t\tdevice_type = \"cpu\";\n" @@ -119,7 +136,7 @@ "> +\t\t\tnext-level-cache = <&A53_L2>;\n" "> \t\t};\n" "> \n" - "> \t\tA53_1: cpu at 101 {\n" + "> \t\tA53_1: cpu@101 {\n" "> @@ -60,6 +63,7 @@\n" "> \t\t\treg = <0x0 0x101>;\n" "> \t\t\tdevice_type = \"cpu\";\n" @@ -127,7 +144,7 @@ "> +\t\t\tnext-level-cache = <&A53_L2>;\n" "> \t\t};\n" "> \n" - "> \t\tA53_2: cpu at 102 {\n" + "> \t\tA53_2: cpu@102 {\n" "> @@ -67,6 +71,7 @@\n" "> \t\t\treg = <0x0 0x102>;\n" "> \t\t\tdevice_type = \"cpu\";\n" @@ -135,7 +152,7 @@ "> +\t\t\tnext-level-cache = <&A53_L2>;\n" "> \t\t};\n" "> \n" - "> \t\tA53_3: cpu at 103 {\n" + "> \t\tA53_3: cpu@103 {\n" "> @@ -74,6 +79,15 @@\n" "> \t\t\treg = <0x0 0x103>;\n" "> \t\t\tdevice_type = \"cpu\";\n" @@ -162,7 +179,7 @@ "> \t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "> +\t\t\tnext-level-cache = <&L2_0>;\n" "> \t\t};\n" - "> \t\tcpu at 1 {\n" + "> \t\tcpu@1 {\n" "> \t\t\tdevice_type = \"cpu\";\n" "> @@ -44,6 +45,7 @@\n" "> \t\t\treg = <0x0 0x1>;\n" @@ -170,7 +187,7 @@ "> \t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "> +\t\t\tnext-level-cache = <&L2_0>;\n" "> \t\t};\n" - "> \t\tcpu at 2 {\n" + "> \t\tcpu@2 {\n" "> \t\t\tdevice_type = \"cpu\";\n" "> @@ -51,6 +53,7 @@\n" "> \t\t\treg = <0x0 0x2>;\n" @@ -178,7 +195,7 @@ "> \t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "> +\t\t\tnext-level-cache = <&L2_0>;\n" "> \t\t};\n" - "> \t\tcpu at 3 {\n" + "> \t\tcpu@3 {\n" "> \t\t\tdevice_type = \"cpu\";\n" "> @@ -58,6 +61,11 @@\n" "> \t\t\treg = <0x0 0x3>;\n" @@ -195,6 +212,10 @@ "> -- \n" "> 1.9.1\n" "> \n" - > + "> \n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -bc72c06b78519a3ec4bceb72888cc7af20026386bb51157916040bc9c6405f84 +70b24bb3cd74d930dac63a8c9d5735563a78d69e33c815c5b0a1b745809df513
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