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From: Chao Peng <chao.p.peng@linux.intel.com>
To: Ian Campbell <Ian.Campbell@citrix.com>
Cc: keir@xen.org, stefano.stabellini@eu.citrix.com,
	andrew.cooper3@citrix.com, Ian.Jackson@eu.citrix.com,
	xen-devel@lists.xen.org, will.auld@intel.com, JBeulich@suse.com,
	wei.liu2@citrix.com
Subject: Re: [PATCH v8 2/5] tools: add routine to get CMT L3 event mask
Date: Thu, 29 Jan 2015 16:32:14 +0800	[thread overview]
Message-ID: <20150129083214.GC3579@pengc-linux.bj.intel.com> (raw)
In-Reply-To: <1422452425.14124.48.camel@citrix.com>

On Wed, Jan 28, 2015 at 01:40:25PM +0000, Ian Campbell wrote:
> On Wed, 2015-01-28 at 16:04 +0800, Chao Peng wrote:
> > This is the tools side wrapper for XEN_SYSCTL_PSR_CMT_get_l3_event_mask
> > of XEN_SYSCTL_psr_cmt_op.
> > 
> > Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
> > ---
> >  tools/libxc/include/xenctrl.h |  1 +
> >  tools/libxc/xc_psr.c          | 17 +++++++++++++++++
> >  tools/libxl/libxl.h           |  1 +
> 
> This needs a LIBXL_HAVE #define in libxl.h to advertise the new
> functionality.
OK.
> 
> > +int xc_psr_cmt_get_l3_event_mask(xc_interface *xch, uint32_t *event_mask);
> 
> What are the possible values of the event mask? Is there a guarantee
> from somewhere that 32-bits is always sufficient?

It comes directly from cpuid which is 32 bit now and look like not
possible to extend it to 64 bit. Only bits[0:2] is used at present.

> 
> How can the libxl caller decode the meaning of the bits since they are
> not defined in the libxl.h header?
> 
> Perhaps a struct of booleans would be a better interface at the libxl
> level?
> 
> Or perhaps the interface should be more along the lines of "is psr
> feature X available", like libxl_psr_..._feature_enabled(ctx,
> SOME_SYMBOL)?
> 
> Or perhaps the function to actual access the info should have an
> ERROR_PSR_FUNCTION NOT_SUPPORTED return?

As answered in another reply, I'd use it as:
int libxl_psr_cmt_type_supported(libxl_ctx *ctx, libxl_psr_cmt_type type);

Thanks,
Chao

  reply	other threads:[~2015-01-29  8:32 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-01-28  8:04 [PATCH v8 0/5] enable Memory Bandwidth Monitoring (MBM) for VMs Chao Peng
2015-01-28  8:04 ` [PATCH v8 1/5] x86: allow reading MSR_IA32_TSC with XENPF_resource_op Chao Peng
2015-01-28 15:42   ` Jan Beulich
2015-01-29  6:35     ` Chao Peng
2015-01-28  8:04 ` [PATCH v8 2/5] tools: add routine to get CMT L3 event mask Chao Peng
2015-01-28 13:40   ` Ian Campbell
2015-01-29  8:32     ` Chao Peng [this message]
2015-01-28  8:04 ` [PATCH v8 3/5] tools: correct coding style for psr Chao Peng
2015-01-28  8:04 ` [PATCH v8 4/5] tools: code refactoring for MBM Chao Peng
2015-01-28  8:04 ` [PATCH v8 5/5] tools, docs: add total/local memory bandwith monitoring Chao Peng
2015-01-28 14:04   ` Ian Campbell
2015-01-28 14:10     ` Ian Jackson
2015-01-28 14:12       ` Ian Campbell
2015-01-29  8:17     ` Chao Peng

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