diff for duplicates of <20150210133734.GC9432@leverpostej> diff --git a/a/1.txt b/N1/1.txt index 7970c97..906656a 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,11 +1,11 @@ On Fri, Feb 06, 2015 at 03:37:52PM +0000, Brent Wang wrote: > Hello Mark, > -> 2015-02-06 18:44 GMT+08:00 Mark Rutland <mark.rutland@arm.com>: +> 2015-02-06 18:44 GMT+08:00 Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>: > > On Fri, Feb 06, 2015 at 08:42:22AM +0000, Brent Wang wrote: > >> Hello Mark, > >> -> >> 2015-02-06 3:30 GMT+08:00 Mark Rutland <mark.rutland@arm.com>: +> >> 2015-02-06 3:30 GMT+08:00 Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>: > >> > On Thu, Feb 05, 2015 at 09:24:37AM +0000, Bintian Wang wrote: > >> >> Add initial dtsi file to support Hisilicon Hi6220 SoC with > >> >> support of Octal core CPUs in two clusters and each cluster @@ -79,7 +79,7 @@ without there being a DTB compatibility issue. > >> >> + reg = <0x0 0xf7032000 0x0 0x1000>; > >> >> + ranges = <0 0x0 0xf7032000 0x1000>; > >> >> + -> >> >> + clock_power: clock3 at 0 { +> >> >> + clock_power: clock3@0 { > >> >> + compatible = "hisilicon,hi6220-clock-power"; > >> >> + reg = <0 0x1000>; > >> >> + #clock-cells = <1>; @@ -93,10 +93,10 @@ without there being a DTB compatibility issue. > >> The SoC clocks are designed and placed under different system controllers, > >> so I define corresponding nodes under different controllers for clock operation. > > -> > What I'm concerned wit hhere is that the pm_ctrl node and the clock3 at 0 +> > What I'm concerned wit hhere is that the pm_ctrl node and the clock3@0 > > sub-node have the _exact_ same register space. > > -> > Given this should mean that the clock3 at 0 node owns that register space, +> > Given this should mean that the clock3@0 node owns that register space, > > having the container node export this as syscon does not make sense. And > > the split between pm_ctrl and clock3@) doesn't seem to make sense given > > they cover the same space. @@ -121,3 +121,7 @@ single node without a child. Thanks, Mark. +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 2617768..6c9b09b 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -4,20 +4,38 @@ "ref\0CAAS=xmgsuY=c8-n_pDiZjLe2u+SPX7msRje7h0sNkRtT3HLfQA@mail.gmail.com\0" "ref\020150206104420.GB9921@leverpostej\0" "ref\0CAAS=xmhcfeQjfyizJa38k+08pbY5WFOZH0a1wEx+gwqgVe0MXw@mail.gmail.com\0" - "From\0mark.rutland@arm.com (Mark Rutland)\0" - "Subject\0[PATCH 3/3] arm64: dts: Add dts files for Hisilicon Hi6220 SoC\0" + "ref\0CAAS=xmhcfeQjfyizJa38k+08pbY5WFOZH0a1wEx+gwqgVe0MXw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org\0" + "From\0Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>\0" + "Subject\0Re: [PATCH 3/3] arm64: dts: Add dts files for Hisilicon Hi6220 SoC\0" "Date\0Tue, 10 Feb 2015 13:37:35 +0000\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Brent Wang <wangbintian-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" + "Cc\0Bintian Wang <bintian.wang-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>" + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org> + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + Catalin Marinas <Catalin.Marinas-5wv7dgnIgG8@public.gmane.org> + Will Deacon <Will.Deacon-5wv7dgnIgG8@public.gmane.org> + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Pawel Moll <Pawel.Moll-5wv7dgnIgG8@public.gmane.org> + ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org> + galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> + khilman-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org <khilman-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + rob.herring-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org <rob.herring-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org <haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + xuwei5-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org <xuwei5-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> + " jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org <o>\0" "\00:1\0" "b\0" "On Fri, Feb 06, 2015 at 03:37:52PM +0000, Brent Wang wrote:\n" "> Hello Mark,\n" "> \n" - "> 2015-02-06 18:44 GMT+08:00 Mark Rutland <mark.rutland@arm.com>:\n" + "> 2015-02-06 18:44 GMT+08:00 Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>:\n" "> > On Fri, Feb 06, 2015 at 08:42:22AM +0000, Brent Wang wrote:\n" "> >> Hello Mark,\n" "> >>\n" - "> >> 2015-02-06 3:30 GMT+08:00 Mark Rutland <mark.rutland@arm.com>:\n" + "> >> 2015-02-06 3:30 GMT+08:00 Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>:\n" "> >> > On Thu, Feb 05, 2015 at 09:24:37AM +0000, Bintian Wang wrote:\n" "> >> >> Add initial dtsi file to support Hisilicon Hi6220 SoC with\n" "> >> >> support of Octal core CPUs in two clusters and each cluster\n" @@ -91,7 +109,7 @@ "> >> >> + reg = <0x0 0xf7032000 0x0 0x1000>;\n" "> >> >> + ranges = <0 0x0 0xf7032000 0x1000>;\n" "> >> >> +\n" - "> >> >> + clock_power: clock3 at 0 {\n" + "> >> >> + clock_power: clock3@0 {\n" "> >> >> + compatible = \"hisilicon,hi6220-clock-power\";\n" "> >> >> + reg = <0 0x1000>;\n" "> >> >> + #clock-cells = <1>;\n" @@ -105,10 +123,10 @@ "> >> The SoC clocks are designed and placed under different system controllers,\n" "> >> so I define corresponding nodes under different controllers for clock operation.\n" "> >\n" - "> > What I'm concerned wit hhere is that the pm_ctrl node and the clock3 at 0\n" + "> > What I'm concerned wit hhere is that the pm_ctrl node and the clock3@0\n" "> > sub-node have the _exact_ same register space.\n" "> >\n" - "> > Given this should mean that the clock3 at 0 node owns that register space,\n" + "> > Given this should mean that the clock3@0 node owns that register space,\n" "> > having the container node export this as syscon does not make sense. And\n" "> > the split between pm_ctrl and clock3@) doesn't seem to make sense given\n" "> > they cover the same space.\n" @@ -132,6 +150,10 @@ "single node without a child.\n" "\n" "Thanks,\n" - Mark. + "Mark.\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -5033970f71104e43bee3ff739e9237664e6623c57bd233e7bce2496b3c6eeb56 +65e852bbb6cc0b1334a597472d347cffe6449e38ecce12a913d76f37518ca558
diff --git a/a/1.txt b/N2/1.txt index 7970c97..eecd88d 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -79,7 +79,7 @@ without there being a DTB compatibility issue. > >> >> + reg = <0x0 0xf7032000 0x0 0x1000>; > >> >> + ranges = <0 0x0 0xf7032000 0x1000>; > >> >> + -> >> >> + clock_power: clock3 at 0 { +> >> >> + clock_power: clock3@0 { > >> >> + compatible = "hisilicon,hi6220-clock-power"; > >> >> + reg = <0 0x1000>; > >> >> + #clock-cells = <1>; @@ -93,10 +93,10 @@ without there being a DTB compatibility issue. > >> The SoC clocks are designed and placed under different system controllers, > >> so I define corresponding nodes under different controllers for clock operation. > > -> > What I'm concerned wit hhere is that the pm_ctrl node and the clock3 at 0 +> > What I'm concerned wit hhere is that the pm_ctrl node and the clock3@0 > > sub-node have the _exact_ same register space. > > -> > Given this should mean that the clock3 at 0 node owns that register space, +> > Given this should mean that the clock3@0 node owns that register space, > > having the container node export this as syscon does not make sense. And > > the split between pm_ctrl and clock3@) doesn't seem to make sense given > > they cover the same space. diff --git a/a/content_digest b/N2/content_digest index 2617768..b9da948 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -4,10 +4,48 @@ "ref\0CAAS=xmgsuY=c8-n_pDiZjLe2u+SPX7msRje7h0sNkRtT3HLfQA@mail.gmail.com\0" "ref\020150206104420.GB9921@leverpostej\0" "ref\0CAAS=xmhcfeQjfyizJa38k+08pbY5WFOZH0a1wEx+gwqgVe0MXw@mail.gmail.com\0" - "From\0mark.rutland@arm.com (Mark Rutland)\0" - "Subject\0[PATCH 3/3] arm64: dts: Add dts files for Hisilicon Hi6220 SoC\0" + "From\0Mark Rutland <mark.rutland@arm.com>\0" + "Subject\0Re: [PATCH 3/3] arm64: dts: Add dts files for Hisilicon Hi6220 SoC\0" "Date\0Tue, 10 Feb 2015 13:37:35 +0000\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Brent Wang <wangbintian@gmail.com>\0" + "Cc\0Bintian Wang <bintian.wang@huawei.com>" + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + Catalin Marinas <Catalin.Marinas@arm.com> + Will Deacon <Will.Deacon@arm.com> + devicetree@vger.kernel.org <devicetree@vger.kernel.org> + robh+dt@kernel.org <robh+dt@kernel.org> + Pawel Moll <Pawel.Moll@arm.com> + ijc+devicetree@hellion.org.uk <ijc+devicetree@hellion.org.uk> + galak@codeaurora.org <galak@codeaurora.org> + khilman@linaro.org <khilman@linaro.org> + mturquette@linaro.org <mturquette@linaro.org> + rob.herring@linaro.org <rob.herring@linaro.org> + zhangfei.gao@linaro.org <zhangfei.gao@linaro.org> + haojian.zhuang@linaro.org <haojian.zhuang@linaro.org> + xuwei5@hisilicon.com <xuwei5@hisilicon.com> + jh80.chung@samsung.com <jh80.chung@samsung.com> + olof@lixom.net <olof@lixom.net> + yanhaifeng@gmail.com <yanhaifeng@gmail.com> + sboyd@codeaurora.org <sboyd@codeaurora.org> + xuejiancheng@huawei.com <xuejiancheng@huawei.com> + sledge.yanwei@huawei.com <sledge.yanwei@huawei.com> + tomeu.vizoso@collabora.com <tomeu.vizoso@collabora.com> + linux@arm.linux.org.uk <linux@arm.linux.org.uk> + guodong.xu@linaro.org <guodong.xu@linaro.org> + xuyiping@hisilicon.com <xuyiping@hisilicon.com> + wangbinghui@hisilicon.com <wangbinghui@hisilicon.com> + zhenwei.wang@hisilicon.com <zhenwei.wang@hisilicon.com> + victor.lixin@hisilicon.com <victor.lixin@hisilicon.com> + puck.chen@hisilicon.com <puck.chen@hisilicon.com> + dan.zhao@hisilicon.com <dan.zhao@hisilicon.com> + huxinwei@huawei.com <huxinwei@huawei.com> + z.liuxinliang@huawei.com <z.liuxinliang@huawei.com> + heyunlei@huawei.com <heyunlei@huawei.com> + kong.kongxinwei@hisilicon.com <kong.kongxinwei@hisilicon.com> + btw@mail.itp.ac.cn <btw@mail.itp.ac.cn> + w.f@huawei.com <w.f@huawei.com> + " liguozhu@hisilicon.com <liguozhu@hisilicon.com>\0" "\00:1\0" "b\0" "On Fri, Feb 06, 2015 at 03:37:52PM +0000, Brent Wang wrote:\n" @@ -91,7 +129,7 @@ "> >> >> + reg = <0x0 0xf7032000 0x0 0x1000>;\n" "> >> >> + ranges = <0 0x0 0xf7032000 0x1000>;\n" "> >> >> +\n" - "> >> >> + clock_power: clock3 at 0 {\n" + "> >> >> + clock_power: clock3@0 {\n" "> >> >> + compatible = \"hisilicon,hi6220-clock-power\";\n" "> >> >> + reg = <0 0x1000>;\n" "> >> >> + #clock-cells = <1>;\n" @@ -105,10 +143,10 @@ "> >> The SoC clocks are designed and placed under different system controllers,\n" "> >> so I define corresponding nodes under different controllers for clock operation.\n" "> >\n" - "> > What I'm concerned wit hhere is that the pm_ctrl node and the clock3 at 0\n" + "> > What I'm concerned wit hhere is that the pm_ctrl node and the clock3@0\n" "> > sub-node have the _exact_ same register space.\n" "> >\n" - "> > Given this should mean that the clock3 at 0 node owns that register space,\n" + "> > Given this should mean that the clock3@0 node owns that register space,\n" "> > having the container node export this as syscon does not make sense. And\n" "> > the split between pm_ctrl and clock3@) doesn't seem to make sense given\n" "> > they cover the same space.\n" @@ -134,4 +172,4 @@ "Thanks,\n" Mark. -5033970f71104e43bee3ff739e9237664e6623c57bd233e7bce2496b3c6eeb56 +714b222183930d28b9e4fff6efe9d2635028995f4d73e2660ea741a7b0b42258
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