From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ying.Liu@freescale.com (Liu Ying) Date: Wed, 11 Feb 2015 22:09:32 +0800 Subject: [PATCH RFC v8 11/21] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver In-Reply-To: <1423659648.4680.18.camel@pengutronix.de> References: <1420014219-915-1-git-send-email-Ying.Liu@freescale.com> <1420014219-915-12-git-send-email-Ying.Liu@freescale.com> <1423131004.3207.27.camel@pengutronix.de> <20150206081318.GA15088@victor> <20150211072128.GA13301@victor> <1423659648.4680.18.camel@pengutronix.de> Message-ID: <20150211140931.GA6666@victor> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Philipp, On Wed, Feb 11, 2015 at 02:00:48PM +0100, Philipp Zabel wrote: > Hi Liu, > > Am Mittwoch, den 11.02.2015, 15:21 +0800 schrieb Liu Ying: > [...] > > Our internal MIPI DSI SoC owner gave me some feedbacks on the clock sources. > > According to him, the Synopsys DesignWare MIPI DSI host controller needs four > > clock sources from an application platform - pclk, refclk, cfg_clk and dpipclk. > > These clocks are mentioned in the "DesignWare Cores MIPI DSI Host Controller > > Databook, 1.01a1.30a.pdf" documentation. > > > > Quote some words from the documentation: > > pclk - APB clock signal. > > refclk - D-PHY reference clock used for Master-side serial clock generation in > > clock multiplying unit(PLL). > > cfg_clk - D-PHY Configuration clock used for the initialization of the PHY. It > > is also used for exiting ULPS state. > > dpipclk - Input Pixel clock signal. > > > > The below table reflects how does i.MX6Q/DL provide the pclk, refclk and cfg_clk > > for the DesignWare MIPI DSI host controller, according to the SoC owner. > > ---------------------------------------------------------------------------- > > | Synopsys | i.MX6Q/DL MIPI DSI | > > | DesignWare |------------------------------------------------------------| > > | documentation | clock | clock root | CCM_CCGR bits | > > |---------------|------------|--------------------|--------------------------| > > | pclk | ips_clk | ipg_clk_root | mipi_core_cfg_clk_enable | > > |---------------|------------|--------------------|--------------------------| > > | refclk | pll_refclk | video_27m_clk_root | mipi_core_cfg_clk_enable | > > |---------------|------------|--------------------|--------------------------| > > | cfg_clk | cfg_clk | video_27m_clk_root | mipi_core_cfg_clk_enable | > > ---------------------------------------------------------------------------- > > > > I think we should add a new clock "IMX6QDL_CLK_MIPI_IPG" as a shared clock gate > > clock. > > That would be necessary if the pclk clock rate mattered or would be set > anywhere. I don't think the pclk clock rate matters a lot. It should be sufficient for the driver only to enable/disable the pclk for registers access, just like the way the pwm-imx driver uses the ipg clock. > > > And, the clock-names property should exactly contain "pclk", "refclk" > > and "cfg_clk", right? > > My personal preference would be to drop the superfluous "clk" prefix if > the resulting clock name is still clearly relatable to the official > name. Existing clock naming for the pclk is a bit mixed - > The "snps,dw-apb-timer" binding uses "pclk", which seems to be quite > common in other places, too. The "snps,dw-apb-uart" bindings use > "apb_pclk". "snps,dw-hdmi-tx" uses "iahb" and "isfr" without the clk > suffix. > How about "pclk", "ref" and "cfg"? Looks good and clear enough. I'd like to use them. Thanks. BTW, regarding the compatible string topic, shall I keep my implementation unchanged and don't append the additional "snps,dw-mipi-dsi" as I shared my concerns about it before? Regards, Liu Ying > > regards > Philipp > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Liu Ying Subject: Re: [PATCH RFC v8 11/21] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver Date: Wed, 11 Feb 2015 22:09:32 +0800 Message-ID: <20150211140931.GA6666@victor> References: <1420014219-915-1-git-send-email-Ying.Liu@freescale.com> <1420014219-915-12-git-send-email-Ying.Liu@freescale.com> <1423131004.3207.27.camel@pengutronix.de> <20150206081318.GA15088@victor> <20150211072128.GA13301@victor> <1423659648.4680.18.camel@pengutronix.de> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <1423659648.4680.18.camel@pengutronix.de> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Philipp Zabel Cc: stefan.wahren@i2se.com, devicetree@vger.kernel.org, linux@arm.linux.org.uk, andyshrk@gmail.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, a.hajda@samsung.com, kernel@pengutronix.de, mturquette@linaro.org, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org SGkgUGhpbGlwcCwKCk9uIFdlZCwgRmViIDExLCAyMDE1IGF0IDAyOjAwOjQ4UE0gKzAxMDAsIFBo aWxpcHAgWmFiZWwgd3JvdGU6Cj4gSGkgTGl1LAo+IAo+IEFtIE1pdHR3b2NoLCBkZW4gMTEuMDIu MjAxNSwgMTU6MjEgKzA4MDAgc2NocmllYiBMaXUgWWluZzoKPiBbLi4uXQo+ID4gT3VyIGludGVy bmFsIE1JUEkgRFNJIFNvQyBvd25lciBnYXZlIG1lIHNvbWUgZmVlZGJhY2tzIG9uIHRoZSBjbG9j ayBzb3VyY2VzLgo+ID4gQWNjb3JkaW5nIHRvIGhpbSwgdGhlIFN5bm9wc3lzIERlc2lnbldhcmUg TUlQSSBEU0kgaG9zdCBjb250cm9sbGVyIG5lZWRzIGZvdXIKPiA+IGNsb2NrIHNvdXJjZXMgZnJv bSBhbiBhcHBsaWNhdGlvbiBwbGF0Zm9ybSAtIHBjbGssIHJlZmNsaywgY2ZnX2NsayBhbmQgZHBp cGNsay4KPiA+IFRoZXNlIGNsb2NrcyBhcmUgbWVudGlvbmVkIGluIHRoZSAiRGVzaWduV2FyZSBD b3JlcyBNSVBJIERTSSBIb3N0IENvbnRyb2xsZXIKPiA+IERhdGFib29rLCAxLjAxYTEuMzBhLnBk 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via listexpand id S1752763AbbBKOEo (ORCPT ); Wed, 11 Feb 2015 09:04:44 -0500 Received: from mail-bl2on0134.outbound.protection.outlook.com ([65.55.169.134]:10021 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751313AbbBKOEl (ORCPT ); Wed, 11 Feb 2015 09:04:41 -0500 Date: Wed, 11 Feb 2015 22:09:32 +0800 From: Liu Ying To: Philipp Zabel CC: , , , , , , , , , Subject: Re: [PATCH RFC v8 11/21] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver Message-ID: <20150211140931.GA6666@victor> References: <1420014219-915-1-git-send-email-Ying.Liu@freescale.com> <1420014219-915-12-git-send-email-Ying.Liu@freescale.com> <1423131004.3207.27.camel@pengutronix.de> <20150206081318.GA15088@victor> <20150211072128.GA13301@victor> <1423659648.4680.18.camel@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <1423659648.4680.18.camel@pengutronix.de> User-Agent: Mutt/1.5.23 (2014-03-12) X-EOPAttributedMessage: 0 Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=Ying.Liu@freescale.com; lists.infradead.org; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:192.88.158.2;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(339900001)(24454002)(51704005)(50986999)(76176999)(33716001)(77096005)(57986006)(93886004)(54356999)(47776003)(33656002)(23726002)(2950100001)(46406003)(86362001)(97756001)(46102003)(110136001)(106466001)(92566002)(77156002)(6806004)(19580395003)(83506001)(85426001)(105606002)(50466002)(87936001)(104016003)(62966003)(217873001);DIR:OUT;SFP:1102;SCL:1;SRVR:BN1PR0301MB0627;H:az84smr01.freescale.net;FPR:;SPF:Fail;MLV:sfv;LANG:en; X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BN1PR0301MB0627; X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004);SRVR:BN1PR0301MB0627; X-Forefront-PRVS: 0484063412 X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:;SRVR:BN1PR0301MB0627; X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2015 14:04:38.3501 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d;Ip=[192.88.158.2] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN1PR0301MB0627 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Philipp, On Wed, Feb 11, 2015 at 02:00:48PM +0100, Philipp Zabel wrote: > Hi Liu, > > Am Mittwoch, den 11.02.2015, 15:21 +0800 schrieb Liu Ying: > [...] > > Our internal MIPI DSI SoC owner gave me some feedbacks on the clock sources. > > According to him, the Synopsys DesignWare MIPI DSI host controller needs four > > clock sources from an application platform - pclk, refclk, cfg_clk and dpipclk. > > These clocks are mentioned in the "DesignWare Cores MIPI DSI Host Controller > > Databook, 1.01a1.30a.pdf" documentation. > > > > Quote some words from the documentation: > > pclk - APB clock signal. > > refclk - D-PHY reference clock used for Master-side serial clock generation in > > clock multiplying unit(PLL). > > cfg_clk - D-PHY Configuration clock used for the initialization of the PHY. It > > is also used for exiting ULPS state. > > dpipclk - Input Pixel clock signal. > > > > The below table reflects how does i.MX6Q/DL provide the pclk, refclk and cfg_clk > > for the DesignWare MIPI DSI host controller, according to the SoC owner. > > ---------------------------------------------------------------------------- > > | Synopsys | i.MX6Q/DL MIPI DSI | > > | DesignWare |------------------------------------------------------------| > > | documentation | clock | clock root | CCM_CCGR bits | > > |---------------|------------|--------------------|--------------------------| > > | pclk | ips_clk | ipg_clk_root | mipi_core_cfg_clk_enable | > > |---------------|------------|--------------------|--------------------------| > > | refclk | pll_refclk | video_27m_clk_root | mipi_core_cfg_clk_enable | > > |---------------|------------|--------------------|--------------------------| > > | cfg_clk | cfg_clk | video_27m_clk_root | mipi_core_cfg_clk_enable | > > ---------------------------------------------------------------------------- > > > > I think we should add a new clock "IMX6QDL_CLK_MIPI_IPG" as a shared clock gate > > clock. > > That would be necessary if the pclk clock rate mattered or would be set > anywhere. I don't think the pclk clock rate matters a lot. It should be sufficient for the driver only to enable/disable the pclk for registers access, just like the way the pwm-imx driver uses the ipg clock. > > > And, the clock-names property should exactly contain "pclk", "refclk" > > and "cfg_clk", right? > > My personal preference would be to drop the superfluous "clk" prefix if > the resulting clock name is still clearly relatable to the official > name. Existing clock naming for the pclk is a bit mixed - > The "snps,dw-apb-timer" binding uses "pclk", which seems to be quite > common in other places, too. The "snps,dw-apb-uart" bindings use > "apb_pclk". "snps,dw-hdmi-tx" uses "iahb" and "isfr" without the clk > suffix. > How about "pclk", "ref" and "cfg"? Looks good and clear enough. I'd like to use them. Thanks. BTW, regarding the compatible string topic, shall I keep my implementation unchanged and don't append the additional "snps,dw-mipi-dsi" as I shared my concerns about it before? Regards, Liu Ying > > regards > Philipp >