From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ying.Liu@freescale.com (Liu Ying) Date: Fri, 13 Feb 2015 10:58:27 +0800 Subject: [PATCH RFC v9 01/20] clk: divider: Correct parent clk round rate if no bestdiv is normally found In-Reply-To: <20150212140625.GA32487@victor> References: <1423720903-24806-1-git-send-email-Ying.Liu@freescale.com> <1423720903-24806-2-git-send-email-Ying.Liu@freescale.com> <20150212093356.GR12209@pengutronix.de> <20150212103944.GA1290@victor> <20150212122405.GW12209@pengutronix.de> <20150212125646.GT8656@n2100.arm.linux.org.uk> <20150212134131.GX12209@pengutronix.de> <20150212140625.GA32487@victor> Message-ID: <20150213025825.GA30014@victor> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Feb 12, 2015 at 10:06:27PM +0800, Liu Ying wrote: > On Thu, Feb 12, 2015 at 02:41:31PM +0100, Sascha Hauer wrote: > > On Thu, Feb 12, 2015 at 12:56:46PM +0000, Russell King - ARM Linux wrote: > > > On Thu, Feb 12, 2015 at 01:24:05PM +0100, Sascha Hauer wrote: > > > > On Thu, Feb 12, 2015 at 06:39:45PM +0800, Liu Ying wrote: > > > > > On Thu, Feb 12, 2015 at 10:33:56AM +0100, Sascha Hauer wrote: > > > > > > On Thu, Feb 12, 2015 at 02:01:24PM +0800, Liu Ying wrote: > > > > > > > If no best divider is normally found, we will try to use the maximum divider. > > > > > > > We should not set the parent clock rate to be 1Hz by force for being rounded. > > > > > > > Instead, we should take the maximum divider as a base and calculate a correct > > > > > > > parent clock rate for being rounded. > > > > > > > > > > > > Please add an explanation why you think the current code is wrong and > > > > > > what this actually fixes, maybe an example? > > > > > > > > > > The MIPI DSI panel's pixel clock rate is 26.4MHz and it's derived from PLL5 on > > > > > the MX6DL SabreSD board. > > > > > > > > > > These are the clock tree summaries with or without the patch applied: > > > > > 1) With the patch applied: > > > > > pll5_bypass_src 1 1 24000000 0 0 > > > > > pll5 1 1 844800048 0 0 > > > > > pll5_bypass 1 1 844800048 0 0 > > > > > pll5_video 1 1 844800048 0 0 > > > > > pll5_post_div 1 1 211200012 0 0 > > > > > pll5_video_div 1 1 211200012 0 0 > > > > > ipu1_di0_pre_sel 1 1 211200012 0 0 > > > > > ipu1_di0_pre 1 1 26400002 0 0 > > > > > ipu1_di0_sel 1 1 26400002 0 0 > > > > > ipu1_di0 1 1 26400002 0 0 > > > > > > > > > > 2) Without the patch applied: > > > > > pll5_bypass_src 1 1 24000000 0 0 > > > > > pll5 1 1 648000000 0 0 > > > > > pll5_bypass 1 1 648000000 0 0 > > > > > pll5_video 1 1 648000000 0 0 > > > > > pll5_post_div 1 1 162000000 0 0 > > > > > pll5_video_div 1 1 40500000 0 0 > > > > > ipu1_di0_pre_sel 1 1 40500000 0 0 > > > > > ipu1_di0_pre 1 1 20250000 0 0 > > > > > ipu1_di0_sel 1 1 20250000 0 0 > > > > > ipu1_di0 1 1 20250000 0 0 > > > > > > > > This seems to be broken since: > > > > > > > > | commit b11d282dbea27db1788893115dfca8a7856bf205 > > > > | Author: Tomi Valkeinen > > > > | Date: Thu Feb 13 12:03:59 2014 +0200 > > > > | > > > > | clk: divider: fix rate calculation for fractional rates > > > > > > > > This patch fixed a case when clk_set_rate(clk_round_rate(rate)) resulted > > > > in a lower frequency than clk_round_rate(rate) returned. > > > > > > > > Since then the MULT_ROUND_UP in clk_divider_bestdiv() is inconsistent to > > > > the rest of the divider. Maybe this should be a simple rate * i now, but > > > > I'm unsure what side effects this has. > > > > > > > > I think your patch only fixes the behaviour in your case by accident, > > > > it's not a correct fix for this issue. > > > > > > Well, it's defined that: > > > > > > new_rate = clk_round_rate(clk, rate); > > > > > > returns the rate which you would get if you did: > > > > > > clk_set_rate(clk, rate); > > > new_rate = clk_get_rate(clk); > > > > > > The reasoning here is that clk_round_rate() gives you a way to query what > > > rate you would get if you were to ask for the rate to be set, without > > > effecting a change in the hardware. > > > > > > The idea that you should call clk_round_rate() first before clk_set_rate() > > > and pass the returned rounded rate into clk_set_rate() is really idiotic > > > given that. Please don't do it, and please remove code which does it, and > > > in review comment on it. Thanks. > > > > Tomis patch is based on the assumption that clk_set_rate(clk_round_rate(rate)) > > is equal to clk_round_rate(rate). So when this assumption is wrong then > > it should simply be reverted. > > So Liu, could you test if reverting Tomis patch fixes your problem? > > Yes, I'll test tomorrow when I have access to my board. Tomi's patch cannot be reverted directly because of conflicts with the later patches. So, I revert all the clock divider driver patches on top of that. And, yes, after reverting Tomi's patch, I may get the correct 26.4MHz pixel clock rate. Regards, Liu Ying > > Regards, > Liu Ying > > > > > Sascha > > > > -- > > Pengutronix e.K. | | > > Industrial Linux Solutions | http://www.pengutronix.de/ | > > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Liu Ying Subject: Re: [PATCH RFC v9 01/20] clk: divider: Correct parent clk round rate if no bestdiv is normally found Date: Fri, 13 Feb 2015 10:58:27 +0800 Message-ID: <20150213025825.GA30014@victor> References: <1423720903-24806-1-git-send-email-Ying.Liu@freescale.com> <1423720903-24806-2-git-send-email-Ying.Liu@freescale.com> <20150212093356.GR12209@pengutronix.de> <20150212103944.GA1290@victor> <20150212122405.GW12209@pengutronix.de> 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([157.56.110.103]:35098 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750973AbbBMCxk (ORCPT ); Thu, 12 Feb 2015 21:53:40 -0500 Date: Fri, 13 Feb 2015 10:58:27 +0800 From: Liu Ying To: Sascha Hauer CC: , , Russell King - ARM Linux , , , , , , Tomi Valkeinen , , , Subject: Re: [PATCH RFC v9 01/20] clk: divider: Correct parent clk round rate if no bestdiv is normally found Message-ID: <20150213025825.GA30014@victor> References: <1423720903-24806-1-git-send-email-Ying.Liu@freescale.com> <1423720903-24806-2-git-send-email-Ying.Liu@freescale.com> <20150212093356.GR12209@pengutronix.de> <20150212103944.GA1290@victor> <20150212122405.GW12209@pengutronix.de> <20150212125646.GT8656@n2100.arm.linux.org.uk> <20150212134131.GX12209@pengutronix.de> <20150212140625.GA32487@victor> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20150212140625.GA32487@victor> User-Agent: Mutt/1.5.23 (2014-03-12) X-EOPAttributedMessage: 0 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=Ying.Liu@freescale.com; lists.infradead.org; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:192.88.168.50;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(339900001)(51704005)(24454002)(86362001)(77096005)(50986999)(15975445007)(92566002)(33716001)(83506001)(87936001)(47776003)(33656002)(54356999)(1720100001)(2950100001)(85426001)(97756001)(76176999)(105606002)(106466001)(110136001)(104016003)(23726002)(46102003)(19580395003)(50466002)(6806004)(57986006)(46406003)(62966003)(19580405001)(77156002)(93886004)(217873001);DIR:OUT;SFP:1102;SCL:1;SRVR:BY2PR0301MB0631;H:tx30smr01.am.freescale.net;FPR:;SPF:Fail;MLV:sfv;LANG:en; X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BY2PR0301MB0631; X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004);SRVR:BY2PR0301MB0631; X-Forefront-PRVS: 0486A0CB86 X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:;SRVR:BY2PR0301MB0631; X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2015 02:53:37.1395 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d;Ip=[192.88.168.50] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2PR0301MB0631 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Feb 12, 2015 at 10:06:27PM +0800, Liu Ying wrote: > On Thu, Feb 12, 2015 at 02:41:31PM +0100, Sascha Hauer wrote: > > On Thu, Feb 12, 2015 at 12:56:46PM +0000, Russell King - ARM Linux wrote: > > > On Thu, Feb 12, 2015 at 01:24:05PM +0100, Sascha Hauer wrote: > > > > On Thu, Feb 12, 2015 at 06:39:45PM +0800, Liu Ying wrote: > > > > > On Thu, Feb 12, 2015 at 10:33:56AM +0100, Sascha Hauer wrote: > > > > > > On Thu, Feb 12, 2015 at 02:01:24PM +0800, Liu Ying wrote: > > > > > > > If no best divider is normally found, we will try to use the maximum divider. > > > > > > > We should not set the parent clock rate to be 1Hz by force for being rounded. > > > > > > > Instead, we should take the maximum divider as a base and calculate a correct > > > > > > > parent clock rate for being rounded. > > > > > > > > > > > > Please add an explanation why you think the current code is wrong and > > > > > > what this actually fixes, maybe an example? > > > > > > > > > > The MIPI DSI panel's pixel clock rate is 26.4MHz and it's derived from PLL5 on > > > > > the MX6DL SabreSD board. > > > > > > > > > > These are the clock tree summaries with or without the patch applied: > > > > > 1) With the patch applied: > > > > > pll5_bypass_src 1 1 24000000 0 0 > > > > > pll5 1 1 844800048 0 0 > > > > > pll5_bypass 1 1 844800048 0 0 > > > > > pll5_video 1 1 844800048 0 0 > > > > > pll5_post_div 1 1 211200012 0 0 > > > > > pll5_video_div 1 1 211200012 0 0 > > > > > ipu1_di0_pre_sel 1 1 211200012 0 0 > > > > > ipu1_di0_pre 1 1 26400002 0 0 > > > > > ipu1_di0_sel 1 1 26400002 0 0 > > > > > ipu1_di0 1 1 26400002 0 0 > > > > > > > > > > 2) Without the patch applied: > > > > > pll5_bypass_src 1 1 24000000 0 0 > > > > > pll5 1 1 648000000 0 0 > > > > > pll5_bypass 1 1 648000000 0 0 > > > > > pll5_video 1 1 648000000 0 0 > > > > > pll5_post_div 1 1 162000000 0 0 > > > > > pll5_video_div 1 1 40500000 0 0 > > > > > ipu1_di0_pre_sel 1 1 40500000 0 0 > > > > > ipu1_di0_pre 1 1 20250000 0 0 > > > > > ipu1_di0_sel 1 1 20250000 0 0 > > > > > ipu1_di0 1 1 20250000 0 0 > > > > > > > > This seems to be broken since: > > > > > > > > | commit b11d282dbea27db1788893115dfca8a7856bf205 > > > > | Author: Tomi Valkeinen > > > > | Date: Thu Feb 13 12:03:59 2014 +0200 > > > > | > > > > | clk: divider: fix rate calculation for fractional rates > > > > > > > > This patch fixed a case when clk_set_rate(clk_round_rate(rate)) resulted > > > > in a lower frequency than clk_round_rate(rate) returned. > > > > > > > > Since then the MULT_ROUND_UP in clk_divider_bestdiv() is inconsistent to > > > > the rest of the divider. Maybe this should be a simple rate * i now, but > > > > I'm unsure what side effects this has. > > > > > > > > I think your patch only fixes the behaviour in your case by accident, > > > > it's not a correct fix for this issue. > > > > > > Well, it's defined that: > > > > > > new_rate = clk_round_rate(clk, rate); > > > > > > returns the rate which you would get if you did: > > > > > > clk_set_rate(clk, rate); > > > new_rate = clk_get_rate(clk); > > > > > > The reasoning here is that clk_round_rate() gives you a way to query what > > > rate you would get if you were to ask for the rate to be set, without > > > effecting a change in the hardware. > > > > > > The idea that you should call clk_round_rate() first before clk_set_rate() > > > and pass the returned rounded rate into clk_set_rate() is really idiotic > > > given that. Please don't do it, and please remove code which does it, and > > > in review comment on it. Thanks. > > > > Tomis patch is based on the assumption that clk_set_rate(clk_round_rate(rate)) > > is equal to clk_round_rate(rate). So when this assumption is wrong then > > it should simply be reverted. > > So Liu, could you test if reverting Tomis patch fixes your problem? > > Yes, I'll test tomorrow when I have access to my board. Tomi's patch cannot be reverted directly because of conflicts with the later patches. So, I revert all the clock divider driver patches on top of that. And, yes, after reverting Tomi's patch, I may get the correct 26.4MHz pixel clock rate. Regards, Liu Ying > > Regards, > Liu Ying > > > > > Sascha > > > > -- > > Pengutronix e.K. | | > > Industrial Linux Solutions | http://www.pengutronix.de/ | > > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel