From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tony Lindgren Subject: Re: [PATCH 0/2] ARM: DRA7x/OMAP5: Clock: DPLL Clock fixes Date: Fri, 6 Mar 2015 08:37:16 -0800 Message-ID: <20150306163715.GO13520@atomide.com> References: <1422724005-9415-1-git-send-email-rk@ti.com> <54E5FC6D.7040701@ti.com> <20150224162719.GA28244@atomide.com> <54ED79B0.4020101@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <54ED79B0.4020101@ti.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Tero Kristo Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, linux@arm.linux.org.uk, Ravikumar Kattekola , pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, linux-kernel@vger.kernel.org, robh+dt@kernel.org, bcousson@baylibre.com, galak@codeaurora.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: linux-omap@vger.kernel.org * Tero Kristo [150225 00:05]: > On 02/24/2015 06:27 PM, Tony Lindgren wrote: > >* Ravikumar Kattekola [150219 08:13]: > >>On 1/31/2015 10:36 PM, Ravikumar Kattekola wrote: > >>>Fix bypass clock source for a few DPLLs. > >>> > >>>On DRA7x/OMAP5, for a few DPLLs, both CLKINP and CLKINPULOW are connected > >>>to a mux and the output from mux is routed to the bypass clkout. > >>>Add a mux-clock as bypass clock with CLKINP and CLKINPULOW as parents. > >>> > >>>Tested against: > >>> tree: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git > >>> branch: master > >>>On: > >>>CPU : OMAP5432 ES2.0 > >>>Board: OMAP5432 uEVM > >>>and > >>>CPU : DRA752 ES1.0 > >>>Board: DRA7xx > >>> > >>> > >>>Ravikumar Kattekola (2): > >>> ARM: DRA7x: dts: Fix the bypass clock source for dpll_iva and others > >>> ARM: OMAP5: dts: Fix the bypass clock source for dpll_iva and others > >>> > >>> arch/arm/boot/dts/dra7xx-clocks.dtsi | 90 ++++++++++++++++++++++++++++---- > >>> arch/arm/boot/dts/omap54xx-clocks.dtsi | 41 +++++++++++++-- > >>> 2 files changed, 118 insertions(+), 13 deletions(-) > >>> > >>Hi Benoit, > >> Can these fixes be looked into for 3.20-rc? > > > >Seem like valid fixes to me. Tero, care to take a look at these and ack > >if OK? > > Yes, both are good to go. > > Acked-by: Tero Kristo Applying both into omap-for-v4.0/fixes thanks. Tony From mboxrd@z Thu Jan 1 00:00:00 1970 From: tony@atomide.com (Tony Lindgren) Date: Fri, 6 Mar 2015 08:37:16 -0800 Subject: [PATCH 0/2] ARM: DRA7x/OMAP5: Clock: DPLL Clock fixes In-Reply-To: <54ED79B0.4020101@ti.com> References: <1422724005-9415-1-git-send-email-rk@ti.com> <54E5FC6D.7040701@ti.com> <20150224162719.GA28244@atomide.com> <54ED79B0.4020101@ti.com> Message-ID: <20150306163715.GO13520@atomide.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org * Tero Kristo [150225 00:05]: > On 02/24/2015 06:27 PM, Tony Lindgren wrote: > >* Ravikumar Kattekola [150219 08:13]: > >>On 1/31/2015 10:36 PM, Ravikumar Kattekola wrote: > >>>Fix bypass clock source for a few DPLLs. > >>> > >>>On DRA7x/OMAP5, for a few DPLLs, both CLKINP and CLKINPULOW are connected > >>>to a mux and the output from mux is routed to the bypass clkout. > >>>Add a mux-clock as bypass clock with CLKINP and CLKINPULOW as parents. > >>> > >>>Tested against: > >>> tree: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git > >>> branch: master > >>>On: > >>>CPU : OMAP5432 ES2.0 > >>>Board: OMAP5432 uEVM > >>>and > >>>CPU : DRA752 ES1.0 > >>>Board: DRA7xx > >>> > >>> > >>>Ravikumar Kattekola (2): > >>> ARM: DRA7x: dts: Fix the bypass clock source for dpll_iva and others > >>> ARM: OMAP5: dts: Fix the bypass clock source for dpll_iva and others > >>> > >>> arch/arm/boot/dts/dra7xx-clocks.dtsi | 90 ++++++++++++++++++++++++++++---- > >>> arch/arm/boot/dts/omap54xx-clocks.dtsi | 41 +++++++++++++-- > >>> 2 files changed, 118 insertions(+), 13 deletions(-) > >>> > >>Hi Benoit, > >> Can these fixes be looked into for 3.20-rc? > > > >Seem like valid fixes to me. Tero, care to take a look at these and ack > >if OK? > > Yes, both are good to go. > > Acked-by: Tero Kristo Applying both into omap-for-v4.0/fixes thanks. Tony From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756059AbbCFQov (ORCPT ); Fri, 6 Mar 2015 11:44:51 -0500 Received: from pmta1.delivery1.ore.mailhop.org ([54.191.214.3]:35942 "EHLO pmta1.delivery1.ore.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753301AbbCFQos (ORCPT ); Fri, 6 Mar 2015 11:44:48 -0500 X-Mail-Handler: DuoCircle Outbound SMTP X-Originating-IP: 104.193.169.186 X-Report-Abuse-To: abuse@duocircle.com (see https://support.duocircle.com/support/solutions/articles/5000540958-duocircle-standard-smtp-abuse-information for abuse reporting information) X-MHO-User: U2FsdGVkX1+AFb7w9Ze6mSAHCsfQ1JAH Date: Fri, 6 Mar 2015 08:37:16 -0800 From: Tony Lindgren To: Tero Kristo Cc: Ravikumar Kattekola , bcousson@baylibre.com, mark.rutland@arm.com, devicetree@vger.kernel.org, linux@arm.linux.org.uk, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, linux-kernel@vger.kernel.org, robh+dt@kernel.org, galak@codeaurora.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 0/2] ARM: DRA7x/OMAP5: Clock: DPLL Clock fixes Message-ID: <20150306163715.GO13520@atomide.com> References: <1422724005-9415-1-git-send-email-rk@ti.com> <54E5FC6D.7040701@ti.com> <20150224162719.GA28244@atomide.com> <54ED79B0.4020101@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <54ED79B0.4020101@ti.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Tero Kristo [150225 00:05]: > On 02/24/2015 06:27 PM, Tony Lindgren wrote: > >* Ravikumar Kattekola [150219 08:13]: > >>On 1/31/2015 10:36 PM, Ravikumar Kattekola wrote: > >>>Fix bypass clock source for a few DPLLs. > >>> > >>>On DRA7x/OMAP5, for a few DPLLs, both CLKINP and CLKINPULOW are connected > >>>to a mux and the output from mux is routed to the bypass clkout. > >>>Add a mux-clock as bypass clock with CLKINP and CLKINPULOW as parents. > >>> > >>>Tested against: > >>> tree: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git > >>> branch: master > >>>On: > >>>CPU : OMAP5432 ES2.0 > >>>Board: OMAP5432 uEVM > >>>and > >>>CPU : DRA752 ES1.0 > >>>Board: DRA7xx > >>> > >>> > >>>Ravikumar Kattekola (2): > >>> ARM: DRA7x: dts: Fix the bypass clock source for dpll_iva and others > >>> ARM: OMAP5: dts: Fix the bypass clock source for dpll_iva and others > >>> > >>> arch/arm/boot/dts/dra7xx-clocks.dtsi | 90 ++++++++++++++++++++++++++++---- > >>> arch/arm/boot/dts/omap54xx-clocks.dtsi | 41 +++++++++++++-- > >>> 2 files changed, 118 insertions(+), 13 deletions(-) > >>> > >>Hi Benoit, > >> Can these fixes be looked into for 3.20-rc? > > > >Seem like valid fixes to me. Tero, care to take a look at these and ack > >if OK? > > Yes, both are good to go. > > Acked-by: Tero Kristo Applying both into omap-for-v4.0/fixes thanks. Tony