From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Arun R Murthy <arun.r.murthy@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 02/12] drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines
Date: Mon, 9 Mar 2015 16:53:09 +0200 [thread overview]
Message-ID: <20150309145309.GS11371@intel.com> (raw)
In-Reply-To: <54FD1815.2020703@intel.com>
On Mon, Mar 09, 2015 at 09:18:37AM +0530, Arun R Murthy wrote:
>
> On Friday 06 March 2015 12:49 AM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Kill the silly DRAIN_LATENCY_PRECISION_* defines and just use the raw
> > number instead.
> >
> > v2: Move the sprite 32/16 -> 16/8 preision multiplier
> > change to another patch (Jesse)
>
> Can this be merged with the previous patch?
Could be, but since it's purely a cosmetic change I think having it
separate keeps the other patch a bit cleaner.
> Also the comments on the patch "[PATCH v2 01/12] drm/i915:
> Reduce CHV DDL multiplier to 16/8" holds good here also.
>
> Thanks and Regards,
> Arun R Murthy
> -------------------
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2015-03-09 14:53 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-05 19:19 [PATCH v2 00/12] drm/i915: Redo VLV/CHV watermark code (v2) ville.syrjala
2015-03-05 19:19 ` [PATCH v2 01/12] drm/i915: Reduce CHV DDL multiplier to 16/8 ville.syrjala
2015-03-09 3:39 ` Arun R Murthy
2015-03-05 19:19 ` [PATCH v2 02/12] drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines ville.syrjala
2015-03-09 3:48 ` Arun R Murthy
2015-03-09 14:53 ` Ville Syrjälä [this message]
2015-03-05 19:19 ` [PATCH 03/12] drm/i915: Simplify VLV drain latency computation ville.syrjala
2015-03-05 19:19 ` [PATCH 04/12] drm/i915: Hide VLV DDL precision handling ville.syrjala
2015-03-09 4:02 ` Arun R Murthy
2015-03-05 19:19 ` [PATCH 05/12] drm/i915: Reorganize VLV DDL setup ville.syrjala
2015-03-05 19:19 ` [PATCH v2 06/12] drm/i915: Pass plane to vlv_compute_drain_latency() ville.syrjala
2015-03-05 19:19 ` [PATCH v2 07/12] drm/i915: Read out display FIFO size on VLV/CHV ville.syrjala
2015-03-05 19:19 ` [PATCH 08/12] drm/i915: Make sure PND deadline mode is enabled " ville.syrjala
2015-03-06 17:29 ` Daniel Vetter
2015-03-05 19:19 ` [PATCH v2 09/12] drm/i915: Rewrite VLV/CHV watermark code ville.syrjala
2015-03-06 17:31 ` Jesse Barnes
2015-03-06 17:40 ` Daniel Vetter
2015-03-06 18:14 ` Ville Syrjälä
2015-03-06 20:28 ` Jesse Barnes
2015-03-10 10:26 ` Daniel Vetter
2015-03-10 11:27 ` Ville Syrjälä
2015-03-05 19:19 ` [PATCH v4 10/12] drm/i915: Program PFI credits for VLV ville.syrjala
2015-03-10 10:05 ` Purushothaman, Vijay A
2015-03-10 10:28 ` Daniel Vetter
2015-03-05 19:19 ` [PATCH v3 11/12] drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV ville.syrjala
2015-03-09 4:23 ` Arun R Murthy
2015-03-05 19:19 ` [PATCH 12/12] drm/i915: Disable DDR DVFS " ville.syrjala
2015-03-06 17:31 ` Jesse Barnes
2015-03-09 4:44 ` Arun R Murthy
2015-03-09 15:00 ` Ville Syrjälä
2015-03-09 15:34 ` Daniel Vetter
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