From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Edgar E. Iglesias" Subject: Re: [PATCH v3 0/2] Add support for Xilinx ZynqMP SoC Date: Wed, 11 Mar 2015 09:59:42 +1000 Message-ID: <20150310235942.GA16866@toto> References: <1425955798-7530-1-git-send-email-edgar.iglesias@gmail.com> <54FED5C2.50903@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <54FED5C2.50903@linaro.org> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Julien Grall Cc: tim@xen.org, stefano.stabellini@citrix.com, ian.campbell@citrix.com, xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org On Tue, Mar 10, 2015 at 11:30:10AM +0000, Julien Grall wrote: > Hello Edgar, > > Thank you for adding support of the ZynqMP. > > On 10/03/15 02:49, Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > > > Adds support for the Cadence UART in Xilinx ZynqMP. The > > rest of the ZynqMP platform is discovered via device-tree. > > Did you make sure that the default grant table range (0xb0000000 - > 0xb0020000) don't overlap with an hardware region? No I didn't, thanks for pointing that out. I need to move these to another address. So now I'm back to needing platform specific code. Long term, Maybe it would make sense making the grant table range somehow configurable via DT? Anyway, I'll send a v4 with the platform code to move the gnt into a reserved area in the memory map. Thanks, Edgar > > Regards, > > -- > Julien Grall