From: Thierry Reding <thierry.reding@gmail.com>
To: Shawn Guo <shawn.guo@linaro.org>
Cc: Gaetan Hug <ghug@induct.be>,
linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org,
fabio.estevam@freescale.com
Subject: Re: [PATCH] pwm: mxs: fix period divider computation
Date: Wed, 11 Mar 2015 11:57:30 +0100 [thread overview]
Message-ID: <20150311105729.GD22149@ulmo.nvidia.com> (raw)
In-Reply-To: <20150302123206.GD3040@dragon>
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On Mon, Mar 02, 2015 at 08:32:09PM +0800, Shawn Guo wrote:
> On Wed, Feb 18, 2015 at 02:06:34PM +0100, Gaetan Hug wrote:
> > The driver computes which clock divider it sould be using from the
> > requested period. This computation assumes that the link between the
> > register value and the actual divider value is raising 2 to the power of
> > the registry value.
> >
> > div = 1 << regvalue
> >
> > This is true only for the first 5 values out of 8. Next values are 64,
> > 256 and, 1024 - instead of 32, 64, 128.
>
> Just checked i.MX28 Reference Manual, and yes, this is the case.
>
> > This affects only the users requesting a period > 0.04369s.
> >
> > Replace the computation with a look-up table.
>
> Your SoB is missing here. Otherwise,
>
> Acked-by: Shawn Guo <shawn.guo@linaro.org>
Gaetan,
can you resend with your Signed-off-by added? Or at least provide it
here? I can't really apply this without one.
Thierry
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prev parent reply other threads:[~2015-03-11 10:57 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-18 13:06 [PATCH] pwm: mxs: fix period divider computation Gaetan Hug
2015-02-18 13:06 ` Gaetan Hug
2015-03-02 12:32 ` Shawn Guo
2015-03-05 1:16 ` Zha, Qipeng
2015-03-11 10:57 ` Thierry Reding [this message]
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