From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bjorn Helgaas Subject: Re: [PATCH v6 10/30] PCI: Introduce pci_host_bridge_list to manage host bridges Date: Thu, 12 Mar 2015 14:56:51 -0500 Message-ID: <20150312195651.GD7346@google.com> References: <1425868467-9667-1-git-send-email-wangyijing@huawei.com> <1425868467-9667-11-git-send-email-wangyijing@huawei.com> <20150312025537.GD10949@google.com> <55018E90.9030301@huawei.com> Mime-Version: 1.0 Return-path: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; bh=eabM7HdJfVE/nb4G3a7g/RmTmm8fDdqkn9hI/8vIKUw=; b=owG43SzH6gBCSGUCCRHTAfUpeyklTWtOMjeoxieNOTcI1AY36esuJGS7Hhcu6PqsgV dK7yailCmHeDKbe1DuaDKOCHhW16jEUWF1+A8WGpTQOU0JrbBrsLml77sdypHpjaGeAk UPwUM4nthClbUXfplRHe1ibuPcrYi2Ytcwn4SJTKpVPqV20tom423zPGkBNf9HQNdBAV wbf8Hj599859vS4/tofShty/dwLgk+rU+pQtNEdj123XGTFodEzIBGrkSterJH2H3yyB dt/e6Q0Rfl156UozT9WMRbtKxrWDwBG87lvkvmQ3nQS6QVAjin0trucZ0xzYUAcg8o6P P1hg== Content-Disposition: inline In-Reply-To: <55018E90.9030301@huawei.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Yijing Wang Cc: Jiang Liu , linux-pci@vger.kernel.org, Yinghai Lu , linux-kernel@vger.kernel.org, Marc Zyngier , linux-arm-kernel@lists.infradead.org, Russell King , x86@kernel.org, Thomas Gleixner , Benjamin Herrenschmidt , Rusty Russell , Tony Luck , linux-ia64@vger.kernel.org, "David S. Miller" , Guan Xuetao , linux-alpha@vger.kernel.org, linux-m68k@lists.linux-m68k.org, Liviu Dudau , Arnd Bergmann , Geert Uytterhoeven On Thu, Mar 12, 2015 at 09:03:12PM +0800, Yijing Wang wrote: > On 2015/3/12 10:55, Bjorn Helgaas wrote: > > On Mon, Mar 09, 2015 at 10:34:07AM +0800, Yijing Wang wrote: > >> Introduce pci_host_bridge_list to manage pci host > >> bridges in system, so we could detect whether > >> the host in domain:bus is alreay registered. > >> Then we could remove bus alreay exist test in > >> __pci_create_root_bus(). > > > > It's a nice idea to move this test into the core. While you're at it, why > > don't you check for any overlap with the bus ranges of existing host > > bridges? For example, if we're trying to create a new host bridge to > > [bus 40-7f], it should conflict with existing bridges to [bus 00-7f] > > as well as to [bus 40-ff]. I think your current patch will detect the > > latter conflict but not the former. > > Now pci host bridge may only know its start bus number, like acpi _BBN provided, > but does not limit the end bus number, Eg. two pci roots report _BBN 0x0 and 0x80, > so we have two bus number resource (0, 0xff) and (0x80, 0xff), if we check it strictly, > some pci scan would fail which currently scan success. _BBN is not the correct source for the bridge's bus number range. There's a comment in acpi_pci_root_add() that explains why: * We need both the start and end of the downstream bus range * to interpret _CBA (MMCONFIG base address), so it really is * supposed to be in _CRS. If we don't find it there, all we * can do is assume [_BBN-0xFF] or [0-0xFF]. A platform SHOULD know the start and and end bus number. If it doesn't I think it's the platform's responsibility to carve up the bus number range. Maybe this can be done by trimming the range of the [bus 00-ff] bridge when we discover another bridge that leads to bus 80. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bjorn Helgaas Date: Thu, 12 Mar 2015 19:56:51 +0000 Subject: Re: [PATCH v6 10/30] PCI: Introduce pci_host_bridge_list to manage host bridges Message-Id: <20150312195651.GD7346@google.com> List-Id: References: <1425868467-9667-1-git-send-email-wangyijing@huawei.com> <1425868467-9667-11-git-send-email-wangyijing@huawei.com> <20150312025537.GD10949@google.com> <55018E90.9030301@huawei.com> In-Reply-To: <55018E90.9030301@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Yijing Wang Cc: Jiang Liu , linux-pci@vger.kernel.org, Yinghai Lu , linux-kernel@vger.kernel.org, Marc Zyngier , linux-arm-kernel@lists.infradead.org, Russell King , x86@kernel.org, Thomas Gleixner , Benjamin Herrenschmidt , Rusty Russell , Tony Luck , linux-ia64@vger.kernel.org, "David S. Miller" , Guan Xuetao , linux-alpha@vger.kernel.org, linux-m68k@vger.kernel.org, Liviu Dudau , Arnd Bergmann , Geert Uytterhoeven On Thu, Mar 12, 2015 at 09:03:12PM +0800, Yijing Wang wrote: > On 2015/3/12 10:55, Bjorn Helgaas wrote: > > On Mon, Mar 09, 2015 at 10:34:07AM +0800, Yijing Wang wrote: > >> Introduce pci_host_bridge_list to manage pci host > >> bridges in system, so we could detect whether > >> the host in domain:bus is alreay registered. > >> Then we could remove bus alreay exist test in > >> __pci_create_root_bus(). > > > > It's a nice idea to move this test into the core. While you're at it, why > > don't you check for any overlap with the bus ranges of existing host > > bridges? For example, if we're trying to create a new host bridge to > > [bus 40-7f], it should conflict with existing bridges to [bus 00-7f] > > as well as to [bus 40-ff]. I think your current patch will detect the > > latter conflict but not the former. > > Now pci host bridge may only know its start bus number, like acpi _BBN provided, > but does not limit the end bus number, Eg. two pci roots report _BBN 0x0 and 0x80, > so we have two bus number resource (0, 0xff) and (0x80, 0xff), if we check it strictly, > some pci scan would fail which currently scan success. _BBN is not the correct source for the bridge's bus number range. There's a comment in acpi_pci_root_add() that explains why: * We need both the start and end of the downstream bus range * to interpret _CBA (MMCONFIG base address), so it really is * supposed to be in _CRS. If we don't find it there, all we * can do is assume [_BBN-0xFF] or [0-0xFF]. A platform SHOULD know the start and and end bus number. If it doesn't I think it's the platform's responsibility to carve up the bus number range. Maybe this can be done by trimming the range of the [bus 00-ff] bridge when we discover another bridge that leads to bus 80. From mboxrd@z Thu Jan 1 00:00:00 1970 From: bhelgaas@google.com (Bjorn Helgaas) Date: Thu, 12 Mar 2015 14:56:51 -0500 Subject: [PATCH v6 10/30] PCI: Introduce pci_host_bridge_list to manage host bridges In-Reply-To: <55018E90.9030301@huawei.com> References: <1425868467-9667-1-git-send-email-wangyijing@huawei.com> <1425868467-9667-11-git-send-email-wangyijing@huawei.com> <20150312025537.GD10949@google.com> <55018E90.9030301@huawei.com> Message-ID: <20150312195651.GD7346@google.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Mar 12, 2015 at 09:03:12PM +0800, Yijing Wang wrote: > On 2015/3/12 10:55, Bjorn Helgaas wrote: > > On Mon, Mar 09, 2015 at 10:34:07AM +0800, Yijing Wang wrote: > >> Introduce pci_host_bridge_list to manage pci host > >> bridges in system, so we could detect whether > >> the host in domain:bus is alreay registered. > >> Then we could remove bus alreay exist test in > >> __pci_create_root_bus(). > > > > It's a nice idea to move this test into the core. While you're at it, why > > don't you check for any overlap with the bus ranges of existing host > > bridges? For example, if we're trying to create a new host bridge to > > [bus 40-7f], it should conflict with existing bridges to [bus 00-7f] > > as well as to [bus 40-ff]. I think your current patch will detect the > > latter conflict but not the former. > > Now pci host bridge may only know its start bus number, like acpi _BBN provided, > but does not limit the end bus number, Eg. two pci roots report _BBN 0x0 and 0x80, > so we have two bus number resource (0, 0xff) and (0x80, 0xff), if we check it strictly, > some pci scan would fail which currently scan success. _BBN is not the correct source for the bridge's bus number range. There's a comment in acpi_pci_root_add() that explains why: * We need both the start and end of the downstream bus range * to interpret _CBA (MMCONFIG base address), so it really is * supposed to be in _CRS. If we don't find it there, all we * can do is assume [_BBN-0xFF] or [0-0xFF]. A platform SHOULD know the start and and end bus number. If it doesn't I think it's the platform's responsibility to carve up the bus number range. Maybe this can be done by trimming the range of the [bus 00-ff] bridge when we discover another bridge that leads to bus 80. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932279AbbCLT47 (ORCPT ); Thu, 12 Mar 2015 15:56:59 -0400 Received: from mail-ob0-f169.google.com ([209.85.214.169]:46614 "EHLO mail-ob0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754184AbbCLT4z (ORCPT ); Thu, 12 Mar 2015 15:56:55 -0400 Date: Thu, 12 Mar 2015 14:56:51 -0500 From: Bjorn Helgaas To: Yijing Wang Cc: Jiang Liu , linux-pci@vger.kernel.org, Yinghai Lu , linux-kernel@vger.kernel.org, Marc Zyngier , linux-arm-kernel@lists.infradead.org, Russell King , x86@kernel.org, Thomas Gleixner , Benjamin Herrenschmidt , Rusty Russell , Tony Luck , linux-ia64@vger.kernel.org, "David S. Miller" , Guan Xuetao , linux-alpha@vger.kernel.org, linux-m68k@vger.kernel.org, Liviu Dudau , Arnd Bergmann , Geert Uytterhoeven Subject: Re: [PATCH v6 10/30] PCI: Introduce pci_host_bridge_list to manage host bridges Message-ID: <20150312195651.GD7346@google.com> References: <1425868467-9667-1-git-send-email-wangyijing@huawei.com> <1425868467-9667-11-git-send-email-wangyijing@huawei.com> <20150312025537.GD10949@google.com> <55018E90.9030301@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <55018E90.9030301@huawei.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 12, 2015 at 09:03:12PM +0800, Yijing Wang wrote: > On 2015/3/12 10:55, Bjorn Helgaas wrote: > > On Mon, Mar 09, 2015 at 10:34:07AM +0800, Yijing Wang wrote: > >> Introduce pci_host_bridge_list to manage pci host > >> bridges in system, so we could detect whether > >> the host in domain:bus is alreay registered. > >> Then we could remove bus alreay exist test in > >> __pci_create_root_bus(). > > > > It's a nice idea to move this test into the core. While you're at it, why > > don't you check for any overlap with the bus ranges of existing host > > bridges? For example, if we're trying to create a new host bridge to > > [bus 40-7f], it should conflict with existing bridges to [bus 00-7f] > > as well as to [bus 40-ff]. I think your current patch will detect the > > latter conflict but not the former. > > Now pci host bridge may only know its start bus number, like acpi _BBN provided, > but does not limit the end bus number, Eg. two pci roots report _BBN 0x0 and 0x80, > so we have two bus number resource (0, 0xff) and (0x80, 0xff), if we check it strictly, > some pci scan would fail which currently scan success. _BBN is not the correct source for the bridge's bus number range. There's a comment in acpi_pci_root_add() that explains why: * We need both the start and end of the downstream bus range * to interpret _CBA (MMCONFIG base address), so it really is * supposed to be in _CRS. If we don't find it there, all we * can do is assume [_BBN-0xFF] or [0-0xFF]. A platform SHOULD know the start and and end bus number. If it doesn't I think it's the platform's responsibility to carve up the bus number range. Maybe this can be done by trimming the range of the [bus 00-ff] bridge when we discover another bridge that leads to bus 80.