diff for duplicates of <20150316002109.GA6640@localhost.localdomain> diff --git a/a/1.txt b/N1/1.txt index f4a875c..a5a3991 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -15,22 +15,22 @@ index b71169e..5c9a118 100644 physicalID = devId750;//either 0x718 or 0x750 physicalRev = revId750; -- if (physicalID = 0x718) +- if (physicalID == 0x718) - { - chip = SM718; - } -- else if (physicalID = 0x750) +- else if (physicalID == 0x750) - { - chip = SM750; -+ if (physicalID = 0x718) ++ if (physicalID == 0x718) + { + chip = SM718; + } -+ else if (physicalID = 0x750) ++ else if (physicalID == 0x750) + { + chip = SM750; /* SM750 and SM750LE are different in their revision ID only. */ - if (physicalRev = SM750LE_REVISION_ID){ + if (physicalRev == SM750LE_REVISION_ID){ chip = SM750LE; } - } @@ -139,7 +139,7 @@ index b71169e..5c9a118 100644 - pll_value_t pll; + pll_value_t pll; #if 1 - if(getChipType() = SM750LE) + if(getChipType() == SM750LE) return MHz(130); #endif @@ -158,7 +158,7 @@ index b71169e..5c9a118 100644 + unsigned int ulActualMxClk; #if 1 /* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */ - if (getChipType() = SM750LE) + if (getChipType() == SM750LE) return; #endif @@ -208,7 +208,7 @@ index b71169e..5c9a118 100644 + unsigned int ulReg, divisor; #if 1 /* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */ - if (getChipType() = SM750LE) + if (getChipType() == SM750LE) return; #endif - if (frequency != 0) @@ -284,7 +284,7 @@ index b71169e..5c9a118 100644 + unsigned int ulReg, divisor; #if 1 /* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */ - if (getChipType() = SM750LE) + if (getChipType() == SM750LE) return; #endif - if (frequency != 0) @@ -396,7 +396,7 @@ index b71169e..5c9a118 100644 @@ -446,11 +446,11 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll) #if 1 - if (getChipType() = SM750LE) + if (getChipType() == SM750LE) - { - /* SM750LE don't have prgrammable PLL and M/N values to work on. - Just return the requested clock. */ @@ -456,10 +456,10 @@ index b71169e..5c9a118 100644 #ifndef VALIDATION_CHIP - /* MXCLK_PLL does not have post divider. */ -- if ((POD > 0) && (pPLL->clockType = MXCLK_PLL)) +- if ((POD > 0) && (pPLL->clockType == MXCLK_PLL)) - break; + /* MXCLK_PLL does not have post divider. */ -+ if ((POD > 0) && (pPLL->clockType = MXCLK_PLL)) ++ if ((POD > 0) && (pPLL->clockType == MXCLK_PLL)) + break; #endif @@ -491,8 +491,8 @@ index b71169e..5c9a118 100644 #endif - /* N has 4 bits [11:8] and its value must between 2 and 15. -- The N = 1 will behave differently --> Result is not correct. */ -- for (N=2; N<\x15; N++) +- The N == 1 will behave differently --> Result is not correct. */ +- for (N=2; N<=15; N++) - { - /* The formula for PLL is ulRequestClk = inputFreq * M / N / (2^OD) - In the following steps, we try to work out a best M value given the others are known. @@ -519,8 +519,8 @@ index b71169e..5c9a118 100644 - pPLL->N = N; - pPLL->OD = OD; + /* N has 4 bits [11:8] and its value must between 2 and 15. -+ The N = 1 will behave differently --> Result is not correct. */ -+ for (N=2; N<\x15; N++) ++ The N == 1 will behave differently --> Result is not correct. */ ++ for (N=2; N<=15; N++) + { + /* The formula for PLL is ulRequestClk = inputFreq * M / N / (2^OD) + In the following steps, we try to work out a best M value given the others are known. @@ -602,10 +602,12 @@ index b71169e..5c9a118 100644 to work out the bit fields in the register. On returning a 32 bit number, the value can be applied to any PLL in the calling function. */ -- ulPllReg - FIELD_SET( 0, PANEL_PLL_CTRL, BYPASS, OFF) +- ulPllReg = +- FIELD_SET( 0, PANEL_PLL_CTRL, BYPASS, OFF) - | FIELD_SET( 0, PANEL_PLL_CTRL, POWER, ON) - | FIELD_SET( 0, PANEL_PLL_CTRL, INPUT, OSC) -+ ulPllReg + FIELD_SET( 0, PANEL_PLL_CTRL, BYPASS, OFF) ++ ulPllReg = ++ FIELD_SET( 0, PANEL_PLL_CTRL, BYPASS, OFF) + | FIELD_SET( 0, PANEL_PLL_CTRL, POWER, ON) + | FIELD_SET( 0, PANEL_PLL_CTRL, INPUT, OSC) #ifndef VALIDATION_CHIP diff --git a/a/content_digest b/N1/content_digest index d8e8e86..007f222 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,6 +1,6 @@ "From\0Ragavendra Nagraj <ragavendra.bn@gmail.com>\0" "Subject\0[PATCH] staging:sm750fb:Fixed no space and indent warnings\0" - "Date\0Mon, 16 Mar 2015 00:21:09 +0000\0" + "Date\0Sun, 15 Mar 2015 17:21:09 -0700\0" "To\0sudipm.mukherjee@gmail.com" teddy.wang@siliconmotion.com gregkh@linuxfoundation.org @@ -26,22 +26,22 @@ " \tphysicalID = devId750;//either 0x718 or 0x750\n" " \tphysicalRev = revId750;\n" " \n" - "- if (physicalID = 0x718)\n" + "- if (physicalID == 0x718)\n" "- {\n" "- chip = SM718;\n" "- }\n" - "- else if (physicalID = 0x750)\n" + "- else if (physicalID == 0x750)\n" "- {\n" "- chip = SM750;\n" - "+\tif (physicalID = 0x718)\n" + "+\tif (physicalID == 0x718)\n" "+\t{\n" "+\t\tchip = SM718;\n" "+\t}\n" - "+\telse if (physicalID = 0x750)\n" + "+\telse if (physicalID == 0x750)\n" "+\t{\n" "+\t\tchip = SM750;\n" " \t\t/* SM750 and SM750LE are different in their revision ID only. */\n" - " \t\tif (physicalRev = SM750LE_REVISION_ID){\n" + " \t\tif (physicalRev == SM750LE_REVISION_ID){\n" " \t\t\tchip = SM750LE;\n" " \t\t}\n" "- }\n" @@ -150,7 +150,7 @@ "- pll_value_t pll;\n" "+\tpll_value_t pll;\n" " #if 1\n" - " \tif(getChipType() = SM750LE)\n" + " \tif(getChipType() == SM750LE)\n" " \t\treturn MHz(130);\n" " #endif\n" " \n" @@ -169,7 +169,7 @@ "+\tunsigned int ulActualMxClk;\n" " #if 1\n" " \t\t/* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */\n" - " \t\tif (getChipType() = SM750LE)\n" + " \t\tif (getChipType() == SM750LE)\n" " \t\t\treturn;\n" " #endif\n" " \n" @@ -219,7 +219,7 @@ "+\tunsigned int ulReg, divisor;\n" " #if 1\n" " \t/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */\n" - " \tif (getChipType() = SM750LE)\n" + " \tif (getChipType() == SM750LE)\n" " \t\treturn;\n" " #endif\n" "- if (frequency != 0)\n" @@ -295,7 +295,7 @@ "+\tunsigned int ulReg, divisor;\n" " #if 1\n" " \t/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */\n" - " \tif (getChipType() = SM750LE)\n" + " \tif (getChipType() == SM750LE)\n" " \t\treturn;\n" " #endif\n" "- if (frequency != 0)\n" @@ -407,7 +407,7 @@ "@@ -446,11 +446,11 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll)\n" " \n" " #if 1\n" - " \tif (getChipType() = SM750LE)\n" + " \tif (getChipType() == SM750LE)\n" "- {\n" "- /* SM750LE don't have prgrammable PLL and M/N values to work on.\n" "- Just return the requested clock. */\n" @@ -467,10 +467,10 @@ " \n" " #ifndef VALIDATION_CHIP\n" "- /* MXCLK_PLL does not have post divider. */\n" - "- if ((POD > 0) && (pPLL->clockType = MXCLK_PLL))\n" + "- if ((POD > 0) && (pPLL->clockType == MXCLK_PLL))\n" "- break;\n" "+\t/* MXCLK_PLL does not have post divider. */\n" - "+\tif ((POD > 0) && (pPLL->clockType = MXCLK_PLL))\n" + "+\tif ((POD > 0) && (pPLL->clockType == MXCLK_PLL))\n" "+\t\tbreak;\n" " #endif\n" " \n" @@ -502,8 +502,8 @@ " #endif\n" " \n" "- /* N has 4 bits [11:8] and its value must between 2 and 15.\n" - "- The N = 1 will behave differently --> Result is not correct. */\n" - "- for (N=2; N<\025; N++)\n" + "- The N == 1 will behave differently --> Result is not correct. */\n" + "- for (N=2; N<=15; N++)\n" "- {\n" "- /* The formula for PLL is ulRequestClk = inputFreq * M / N / (2^OD)\n" "- In the following steps, we try to work out a best M value given the others are known.\n" @@ -530,8 +530,8 @@ "- pPLL->N = N;\n" "- pPLL->OD = OD;\n" "+\t\t/* N has 4 bits [11:8] and its value must between 2 and 15.\n" - "+\t\tThe N = 1 will behave differently --> Result is not correct. */\n" - "+\tfor (N=2; N<\025; N++)\n" + "+\t\tThe N == 1 will behave differently --> Result is not correct. */\n" + "+\tfor (N=2; N<=15; N++)\n" "+\t\t{\n" "+\t\t/* The formula for PLL is ulRequestClk = inputFreq * M / N / (2^OD)\n" "+\t\tIn the following steps, we try to work out a best M value given the others are known.\n" @@ -613,10 +613,12 @@ " to work out the bit fields in the register.\n" " On returning a 32 bit number, the value can be applied to any PLL in the calling function.\n" " */\n" - "- ulPllReg - FIELD_SET( 0, PANEL_PLL_CTRL, BYPASS, OFF)\n" + "- ulPllReg =\n" + "- FIELD_SET( 0, PANEL_PLL_CTRL, BYPASS, OFF)\n" "- | FIELD_SET( 0, PANEL_PLL_CTRL, POWER, ON)\n" "- | FIELD_SET( 0, PANEL_PLL_CTRL, INPUT, OSC)\n" - "+\tulPllReg +\tFIELD_SET( 0, PANEL_PLL_CTRL, BYPASS, OFF)\n" + "+\tulPllReg =\n" + "+\tFIELD_SET( 0, PANEL_PLL_CTRL, BYPASS, OFF)\n" "+\t| FIELD_SET( 0, PANEL_PLL_CTRL, POWER, ON)\n" "+\t| FIELD_SET( 0, PANEL_PLL_CTRL, INPUT, OSC)\n" " #ifndef VALIDATION_CHIP\n" @@ -638,4 +640,4 @@ "-- \n" 1.7.10.4 -7db9fd3b00dd811716153a77b44bc6a501f9554560641ecf463fb866ff9c3d1c +d96d75328bc3c6b9a5f5410bb6edb66a146bf39b0745977b054df2e14b150405
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