From: Nicolin Chen <nicoleotsuka@gmail.com>
To: Xuebing Wang <xbing6@gmail.com>
Cc: alsa-devel@alsa-project.org,
niranjan Patil <Niranjan.Patil@infocus.com>,
Richard Jiang <Richard.Jiang@infocus.com>
Subject: Re: Can iMX6SL supports different sampling rate for different SSIs?
Date: Mon, 16 Mar 2015 17:38:30 -0700 [thread overview]
Message-ID: <20150317003830.GA552@Asurada-GSX> (raw)
In-Reply-To: <5507743B.5040808@gmail.com>
On Tue, Mar 17, 2015 at 08:24:27AM +0800, Xuebing Wang wrote:
> 2) As pll4_main_clk is global for all 3 SSIs, I think that we can *not* use
> 8k for ssi1 and 44.1k for ssi2, right? Because 8k and 44.1k requires
> different pll4 clock, right?
True.
> -- However, as 48k, 32k, 16k, 8k can use same pll4, thus different SSI
> can use different sampling rate in this subset (48k, 32k, 16k, 8k).
> -- Same principle applies for 44.1k, 22.050, 11.025 subset of sampling
> rates.
Correct. You need to choose 48K-group or 44.1K-group if only using PLL4.
If you are so obsessed with full sample rate support in hardware level,
you might need to do a trade-off like sacrificing video function -- you
would then be allowed to use PLL5 to forge a rate for another rate group.
I forgot if PLL3, another possible parent clock of SSI, is suitable for
one of the groups. You may also take a look at it.
Nicolin
next prev parent reply other threads:[~2015-03-17 0:38 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-17 0:24 Can iMX6SL supports different sampling rate for different SSIs? Xuebing Wang
2015-03-17 0:38 ` Nicolin Chen [this message]
2015-03-17 0:45 ` Xuebing Wang
2015-03-19 23:13 ` Xuebing Wang
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