Re: [PATCH 3/6] X86: improve psr scheduling code

[Chao Peng <chao.p.peng@linux.intel.com>]

On Mon, Mar 16, 2015 at 04:53:35PM +0000, Jan Beulich wrote:
> >>> On 13.03.15 at 11:13, <chao.p.peng@linux.intel.com> wrote:
> > @@ -1473,11 +1471,10 @@ static void __context_switch(void)
> >          }
> >          vcpu_restore_fpu_eager(n);
> >          n->arch.ctxt_switch_to(n);
> > -
> > -        if ( psr_cmt_enabled() && n->domain->arch.psr_rmid > 0 )
> > -            psr_assoc_rmid(n->domain->arch.psr_rmid);
> >      }
> >  
> > +    psr_ctxt_switch_to(n->domain);
> 
> But you now potentially do the MSR write despite it already being
> the needed value (e.g. when switching between an idle vCPU and
> another one also having RMID zero).

Not really. The MSR is already updated lazily in psr_assoc_rmid().

Chao