Re: [Patch v5] x86: irq_comm: Add check for RH bit in kvm_set_msi_irq

["Radim Krčmář" <rkrcmar@redhat.com>]

2015-03-18 22:09-0300, Marcelo Tosatti:
> > > See native_compose_msi_msg:
> > >                 ((apic->irq_dest_mode == 0) ?
> > >                         MSI_ADDR_DEST_MODE_PHYSICAL :
> > >                         MSI_ADDR_DEST_MODE_LOGICAL) |
> > >                 ((apic->irq_delivery_mode != dest_LowestPrio) ?
> > >                         MSI_ADDR_REDIRECTION_CPU :
> > >                         MSI_ADDR_REDIRECTION_LOWPRI) |
> > > So it does configure DM = MSI_ADDR_DEST_MODE_LOGICAL
> > > and RH = MSI_ADDR_REDIRECTION_LOWPRI.
> > ...and yet this is a good counterexample against my argument :)

(It could be just to make the code nicer ... the developer might have
 known how real hardware will handle it.)

> > What I think I'll do is revert this particular change so that dest_mode is
> > set independently of RH. While I'm not entirely convinced that this is the
> > intended interpretation, I do think that consistency with the existing logic
> > is probably desirable for the time being. If I can get closure on the matter
> > I'll re-submit that change, but for the time being I will undo it.
> Just write MSI-X table entries on real hardware (say: modify
> native_compose_msi_msg or MSI-X equivalent), with all RH/DM
> combinations, and see what behaviour is
> comes up?  

I second this idea.
(We'd also get to know how RH interacts with delivery mode.)

https://software.intel.com/en-us/forums/topic/288883
said that DM=1+RH=0 delivers to physical:

  The exact quote from 10.11.1 is "When RH is 0, the interrupt is
  directed to the processor listed in the Destination ID field."
  This does not specify if physical or logical addressing mode is used.

  Experimentation shows that physical addressing mode is used
  with RH equal to zero.

and it also mentioned a disturbing behavior, which I chose to ignore:

  10.11.1 goes on to say that "When RH is 1 and the physical destination
  mode is used [i.e., DM = 0], the Destination ID field must not be set
  to 0xFF; it must point to a processor that is present and enabled to
  receive the interrupt."

  This would seem to be the exact same case as RH equal to zero;
  there, DM is ignored: "If RH is 0, then the DM bit is
  ignored and the message is sent ahead independent of whether
  the physical or logical destination mode is used."

  However, changing RH to 1 and DM to zero fails to send the message
  to the physical processor.