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From: Ingo Molnar <mingo@kernel.org>
To: "K. Y. Srinivasan" <kys@microsoft.com>
Cc: x86@kernel.org, gregkh@linuxfoundation.org,
	linux-kernel@vger.kernel.org, devel@linuxdriverproject.org,
	olaf@aepfle.de, apw@canonical.com, jasowang@redhat.com,
	tglx@linutronix.de, hpa@zytor.com
Subject: Re: [PATCH V2 1/1] X86: hyperv: Enable MSR based APIC access
Date: Wed, 25 Mar 2015 13:15:14 +0100	[thread overview]
Message-ID: <20150325121514.GB2542@gmail.com> (raw)
In-Reply-To: <1426714696-8557-1-git-send-email-kys@microsoft.com>


* K. Y. Srinivasan <kys@microsoft.com> wrote:

> If the hypervisor supports MSR based access to the APIC registers
> (EOI, TPR and ICR), implement the MSR based access.
> 
> Signed-off-by: K. Y. Srinivasan <kys@microsoft.com>
> ---
>  Changes from V1: Addressed comments from Ingo Molnar <mingo.kernel.org@gmail.com>

You didn't address my primary feedback:

> > So since we are trying to explain things, wouldn't this comment be 
> > more informative if it explained why we are trying to use the 
> > x2APIC facilities of Hyper-V?
> >
> > I.e. what are the benefits of using the x2apic API towards the 
> > hypervisor?

please explain the purpose, context and benefits, not just what the 
patch does - even if the comment from your first patch is now gone.

Thanks,

	Ingo

  reply	other threads:[~2015-03-25 12:15 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-18 21:38 [PATCH V2 1/1] X86: hyperv: Enable MSR based APIC access K. Y. Srinivasan
2015-03-25 12:15 ` Ingo Molnar [this message]
2015-03-25 16:27   ` KY Srinivasan

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