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Date:   Fri, 27 Mar 2015 13:04:05 +0100
From:   Ralf Baechle <ralf@linux-mips.org>
To:     Florian Fainelli <f.fainelli@gmail.com>
Cc:     linux-mips@linux-mips.org, cernekee@gmail.com,
        jaedon.shin@gmail.com
Subject: Re: [PATCH 1/2] MIPS: BMIPS: Flush the readahead cache after DMA
Message-ID: <20150327120405.GP1385@linux-mips.org>
References: <1427345715-16516-1-git-send-email-f.fainelli@gmail.com>
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On Wed, Mar 25, 2015 at 09:55:14PM -0700, Florian Fainelli wrote:

> From: Kevin Cernekee <cernekee@gmail.com>
> 
> BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
> the L1/L2.  During a DMA operation, accesses adjacent to a DMA buffer
> may cause parts of the DMA buffer to be prefetched into the RAC.  To
> avoid possible coherency problems, flush the RAC upon DMA completion.
> 
> Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  arch/mips/include/asm/bmips.h |  2 +-
>  arch/mips/mm/dma-default.c    | 15 +++++++++++++++
>  2 files changed, 16 insertions(+), 1 deletion(-)

I'm not keen on including platform-specific files that may blow up on
another platform.  So what I suggest instead is something like rewriting
cpu_needs_post_dma_flush() to invoke a platform-specific hook function
plat_post_dma_flush() which would be defined in <asm/dma-coherence.h>
rsp. <mach/dma-coherence.h>.

I'm going to whip up something.

  Ralf