From: Andi Kleen <andi@firstfloor.org>
To: "Liang, Kan" <kan.liang@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"mingo@kernel.org" <mingo@kernel.org>,
"acme@infradead.org" <acme@infradead.org>,
"eranian@google.com" <eranian@google.com>,
"andi@firstfloor.org" <andi@firstfloor.org>
Subject: Re: [PATCH V5 4/6] perf, x86: handle multiple records in PEBS buffer
Date: Mon, 30 Mar 2015 19:25:45 +0200 [thread overview]
Message-ID: <20150330172545.GG2366@two.firstfloor.org> (raw)
In-Reply-To: <37D7C6CF3E00A74B8858931C1DB2F0770178BAF5@SHSMSX103.ccr.corp.intel.com>
> > - its possible (and harmless) for the status field to contain set bits
> > for !PEBS events -- the proposed code is buggy here.
> I will fix it.
> > - its possible to have multiple PEBS bits set even though the event
> > really only was for a single event -- if you count everything with
> > multiple PEBS bits set as a collision you're counting wrong.
> >
>
> In what situation multiple PEBS bits was set for a single event?
> Could you please give me an example?
The field in the PEBS record is just a copy of GLOBAL_STATUS (minus
some extra bits), so if there were already bits in GLOBAL_STATUS
that haven't been cleared yet you may see multiple bits
In a proper configuration this should be rare, as we expect the
events to be different and run on different effective frequencies,
so GLOBAL_STATUS should be already cleared.
-Andi
--
ak@linux.intel.com -- Speaking for myself only.
next prev parent reply other threads:[~2015-03-30 17:25 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-23 14:25 [PATCH V5 0/6] large PEBS interrupt threshold Kan Liang
2015-02-23 14:25 ` [PATCH V5 1/6] perf, x86: use the PEBS auto reload mechanism when possible Kan Liang
2015-03-30 12:06 ` Peter Zijlstra
2015-03-30 14:02 ` Peter Zijlstra
2015-02-23 14:25 ` [PATCH V5 2/6] perf, x86: introduce setup_pebs_sample_data() Kan Liang
2015-02-23 14:25 ` [PATCH V5 3/6] perf, x86: large PEBS interrupt threshold Kan Liang
2015-03-02 17:08 ` Stephane Eranian
2015-03-02 17:59 ` Andi Kleen
2015-03-02 18:07 ` Stephane Eranian
2015-03-30 13:54 ` Peter Zijlstra
2015-02-23 14:25 ` [PATCH V5 4/6] perf, x86: handle multiple records in PEBS buffer Kan Liang
2015-03-30 13:45 ` Peter Zijlstra
2015-03-30 17:19 ` Liang, Kan
2015-03-30 17:25 ` Andi Kleen [this message]
2015-03-30 17:43 ` Liang, Kan
2015-03-30 17:45 ` Andi Kleen
2015-03-30 20:07 ` Peter Zijlstra
2015-03-30 20:11 ` Andi Kleen
2015-03-30 21:24 ` Peter Zijlstra
2015-03-30 21:53 ` Andi Kleen
2015-02-23 14:25 ` [PATCH V5 5/6] perf, x86: drain PEBS buffer during context switch Kan Liang
2015-03-30 13:50 ` Peter Zijlstra
2015-02-23 14:25 ` [PATCH V5 6/6] perf, x86: enlarge PEBS buffer Kan Liang
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