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Date:   Wed, 8 Apr 2015 00:45:01 +0200
From:   Ralf Baechle <ralf@linux-mips.org>
To:     "Maciej W. Rozycki" <macro@linux-mips.org>
Cc:     linux-mips@linux-mips.org
Subject: Re: [PATCH 47/48] MIPS: Respect the ISA level in FCSR handling
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On Tue, Apr 07, 2015 at 10:13:38PM +0100, Maciej W. Rozycki wrote:

> > > Index: linux/arch/mips/include/asm/fpu.h
> > > ===================================================================
> > > --- linux.orig/arch/mips/include/asm/fpu.h	2015-04-02 20:18:47.499480000 +0100
> > > +++ linux/arch/mips/include/asm/fpu.h	2015-04-02 20:27:59.745241000 +0100
> > > @@ -14,6 +14,7 @@
> > >  #include <linux/thread_info.h>
> > >  #include <linux/bitops.h>
> > >  
> > > +#include <asm/current.h>
> > >  #include <asm/mipsregs.h>
> > >  #include <asm/cpu.h>
> > >  #include <asm/cpu-features.h>
> > 
> > This is adding a 2nd inclusion of <asm/current.h>.  Will fix that.
> 
>  Thanks!  I resisted the temptation to include changes to sort inclusions 
> with this series or it would risk becoming an ever going effort.  Though 
> it would have avoided an oversight like this.

I found it only because once in a blue moon I run the various checkers
that ship with the kernel.  Turns out half of them don't work out of
the box, at least not for my setup so there's yet more work to do.

  Ralf