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Date: Fri, 10 Apr 2015 09:30:15 +1000
From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
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Subject: Re: [Qemu-devel] [RFC PATCH 0/3] pflash_cfi01: allow
 reading/writing it only in secure mode
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To: Paolo Bonzini <pbonzini@redhat.com>
Cc: Peter Maydell <peter.maydell@linaro.org>, Peter Crosthwaite <peter.crosthwaite@xilinx.com>, Laszlo Ersek <lersek@redhat.com>, QEMU Developers <qemu-devel@nongnu.org>, Gerd Hoffmann <kraxel@redhat.com>

On Thu, Apr 09, 2015 at 06:27:42PM +0200, Paolo Bonzini wrote:
> 
> 
> On 09/04/2015 18:10, Laszlo Ersek wrote:
> > In OVMF, the reset vector and the SEC phase code run from (read-only)
> > flash. SEC decompresses everything else to RAM. Also, SEC does not
> > access read-write flash (the varstore) at all.
> > 
> > The above is a specialty of OVMF. In ArmVirtualizationQemu (aka AAVMF),
> > two further module types run from flash, after SEC: PEI_CORE, and some
> > PEIMs (ie. the PEI phase comes into the picture). During PEI, read-only
> > access to the varstore should be supported.
> 
> Read-only access should always be fine (though with a tweak to these
> patches, and slower---because it exits to QEMU---if another CPU is
> looking at the flash in MMIO mode).  The problem is execution.
> 
> But on x86 flash should never be accessed by multiple CPUs at the same
> time, unless all of them know that the flash is in ROM mode.
> 
> As I understand it, on ARM secure (EL3) and non-secure (EL<3) modes have
> effectively different address spaces.  Therefore, one EL3 CPU could put
> the flash in MMIO mode for programming, while another EL1 CPU could be
> reading from the flash in ROM mode.  In QEMU, this could be implemented
> with two memory regions and per-CPU address spaces.  These patches
> should not get in the way, but they would not be useful.

Right, that matches my understanding.

Thanks,
Edgar