* [PATCH 0/2] Add support for PL172 memory-controller @ 2015-04-28 17:24 ` Joachim Eastwood 0 siblings, 0 replies; 12+ messages in thread From: Joachim Eastwood @ 2015-04-28 17:24 UTC (permalink / raw) To: linux-arm-kernel This patch set adds support for setting up static memory devices on a ARM PrimeCell MultiPort Memory Controller (PL172) from DT. Dynamic memory (SDRAM) is not supported in this patch set. DT bindings for PL172 is based on the bindings for the TI AEMIF memory controller. PL172 can be found on a number of NXP devices like the LPC18xx family. Tested on Embedded Artists' LPC4357 Developer's Kit with NOR Flash (SST39VF320) and 74LCV16374 (gpio-74x164) on MPMC. Joachim Eastwood (2): memory: add ARM PL172 MultiPort Memory Controller driver doc: dt: add documentation for pl172 memory bindings .../bindings/memory-controllers/arm,pl172.txt | 125 +++++++++ drivers/memory/Kconfig | 8 + drivers/memory/Makefile | 1 + drivers/memory/pl172.c | 302 +++++++++++++++++++++ 4 files changed, 436 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt create mode 100644 drivers/memory/pl172.c -- 1.8.0 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 0/2] Add support for PL172 memory-controller @ 2015-04-28 17:24 ` Joachim Eastwood 0 siblings, 0 replies; 12+ messages in thread From: Joachim Eastwood @ 2015-04-28 17:24 UTC (permalink / raw) To: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, arnd-r2nGTMty4D4, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Cc: linux-lFZ/pmaqli7XmaaqVzeoHQ, will.deacon-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, grant.likely-QSEj5FYQhm4dnm+yROfE0A, Joachim Eastwood This patch set adds support for setting up static memory devices on a ARM PrimeCell MultiPort Memory Controller (PL172) from DT. Dynamic memory (SDRAM) is not supported in this patch set. DT bindings for PL172 is based on the bindings for the TI AEMIF memory controller. PL172 can be found on a number of NXP devices like the LPC18xx family. Tested on Embedded Artists' LPC4357 Developer's Kit with NOR Flash (SST39VF320) and 74LCV16374 (gpio-74x164) on MPMC. Joachim Eastwood (2): memory: add ARM PL172 MultiPort Memory Controller driver doc: dt: add documentation for pl172 memory bindings .../bindings/memory-controllers/arm,pl172.txt | 125 +++++++++ drivers/memory/Kconfig | 8 + drivers/memory/Makefile | 1 + drivers/memory/pl172.c | 302 +++++++++++++++++++++ 4 files changed, 436 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt create mode 100644 drivers/memory/pl172.c -- 1.8.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/2] memory: add ARM PL172 MultiPort Memory Controller driver @ 2015-04-28 17:24 ` Joachim Eastwood 0 siblings, 0 replies; 12+ messages in thread From: Joachim Eastwood @ 2015-04-28 17:24 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Joachim Eastwood <manabian@gmail.com> --- drivers/memory/Kconfig | 8 ++ drivers/memory/Makefile | 1 + drivers/memory/pl172.c | 302 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 311 insertions(+) create mode 100644 drivers/memory/pl172.c diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 868036f70f8f..f69a8842ec69 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -7,6 +7,14 @@ menuconfig MEMORY if MEMORY +config ARM_PL172_MPMC + tristate "ARM PL172 MPMC driver" + depends on ARM_AMBA && OF + help + This selects the ARM PrimeCell PL172 MultiPort Memory Controller. + If you have an embedded system with an AMBA bus and a PL172 + controller, say Y or M here. + config ATMEL_SDRAMC bool "Atmel (Multi-port DDR-)SDRAM Controller" default y diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index b670441e3cdf..1c46af501610 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -5,6 +5,7 @@ ifeq ($(CONFIG_DDR),y) obj-$(CONFIG_OF) += of_memory.o endif +obj-$(CONFIG_ARM_PL172_MPMC) += pl172.o obj-$(CONFIG_ATMEL_SDRAMC) += atmel-sdramc.o obj-$(CONFIG_TI_AEMIF) += ti-aemif.o obj-$(CONFIG_TI_EMIF) += emif.o diff --git a/drivers/memory/pl172.c b/drivers/memory/pl172.c new file mode 100644 index 000000000000..552f92da9369 --- /dev/null +++ b/drivers/memory/pl172.c @@ -0,0 +1,302 @@ +/* + * Memory controller driver for ARM PrimeCell PL172 + * PrimeCell MultiPort Memory Controller (PL172) + * + * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com> + * + * Based on: + * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/amba/bus.h> +#include <linux/clk.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/time.h> + +#define MPMC_STATIC_CFG(n) (0x200 + 0x20 * n) +#define MPMC_STATIC_CFG_MW_8BIT 0x0 +#define MPMC_STATIC_CFG_MW_16BIT 0x1 +#define MPMC_STATIC_CFG_MW_32BIT 0x2 +#define MPMC_STATIC_CFG_PM BIT(3) +#define MPMC_STATIC_CFG_PC BIT(6) +#define MPMC_STATIC_CFG_PB BIT(7) +#define MPMC_STATIC_CFG_EW BIT(8) +#define MPMC_STATIC_CFG_B BIT(19) +#define MPMC_STATIC_CFG_P BIT(20) +#define MPMC_STATIC_WAIT_WEN(n) (0x204 + 0x20 * n) +#define MPMC_STATIC_WAIT_WEN_MAX 0x0f +#define MPMC_STATIC_WAIT_OEN(n) (0x208 + 0x20 * n) +#define MPMC_STATIC_WAIT_OEN_MAX 0x0f +#define MPMC_STATIC_WAIT_RD(n) (0x20c + 0x20 * n) +#define MPMC_STATIC_WAIT_RD_MAX 0x1f +#define MPMC_STATIC_WAIT_PAGE(n) (0x210 + 0x20 * n) +#define MPMC_STATIC_WAIT_PAGE_MAX 0x1f +#define MPMC_STATIC_WAIT_WR(n) (0x214 + 0x20 * n) +#define MPMC_STATIC_WAIT_WR_MAX 0x1f +#define MPMC_STATIC_WAIT_TURN(n) (0x218 + 0x20 * n) +#define MPMC_STATIC_WAIT_TURN_MAX 0x0f + +/* Maximum number of static chip selects */ +#define PL172_MAX_CS 4 + +struct pl172_data { + void __iomem *base; + unsigned long rate; + struct clk *clk; +}; + +static int pl172_timing_prop(struct amba_device *adev, + const struct device_node *np, const char *name, + u32 reg_offset, u32 max, int start) +{ + struct pl172_data *pl172 = amba_get_drvdata(adev); + int cycles; + u32 val; + + if (!of_property_read_u32(np, name, &val)) { + cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; + if (cycles < 0) { + cycles = 0; + } else if (cycles > max) { + dev_err(&adev->dev, "%s timing too tight\n", name); + return -EINVAL; + } + + writel(cycles, pl172->base + reg_offset); + } + + dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start + + readl(pl172->base + reg_offset)); + + return 0; +} + +static int pl172_setup_static(struct amba_device *adev, + struct device_node *np, u32 cs) +{ + struct pl172_data *pl172 = amba_get_drvdata(adev); + u32 cfg; + int ret; + + /* MPMC static memory configuration */ + if (!of_property_read_u32(np, "mpmc,memory-width", &cfg)) { + if (cfg == 8) { + cfg = MPMC_STATIC_CFG_MW_8BIT; + } else if (cfg == 16) { + cfg = MPMC_STATIC_CFG_MW_16BIT; + } else if (cfg == 32) { + cfg = MPMC_STATIC_CFG_MW_32BIT; + } else { + dev_err(&adev->dev, "invalid memory width cs%u\n", cs); + return -EINVAL; + } + } else { + dev_err(&adev->dev, "memory-width property required\n"); + return -EINVAL; + } + + if (of_property_read_bool(np, "mpmc,async-page-mode")) + cfg |= MPMC_STATIC_CFG_PM; + + if (of_property_read_bool(np, "mpmc,cs-active-high")) + cfg |= MPMC_STATIC_CFG_PC; + + if (of_property_read_bool(np, "mpmc,byte-lane-low")) + cfg |= MPMC_STATIC_CFG_PB; + + if (of_property_read_bool(np, "mpmc,extended-wait")) + cfg |= MPMC_STATIC_CFG_EW; + + if (of_property_read_bool(np, "mpmc,buffer-enable")) + cfg |= MPMC_STATIC_CFG_B; + + if (of_property_read_bool(np, "mpmc,write-protect")) + cfg |= MPMC_STATIC_CFG_P; + + writel(cfg, pl172->base + MPMC_STATIC_CFG(cs)); + dev_dbg(&adev->dev, "mpmc static config cs%u: 0x%08x\n", cs, cfg); + + /* MPMC static memory timing */ + ret = pl172_timing_prop(adev, np, "mpmc,write-enable-delay", + MPMC_STATIC_WAIT_WEN(cs), + MPMC_STATIC_WAIT_WEN_MAX, 1); + if (ret) + goto fail; + + ret = pl172_timing_prop(adev, np, "mpmc,output-enable-delay", + MPMC_STATIC_WAIT_OEN(cs), + MPMC_STATIC_WAIT_OEN_MAX, 0); + if (ret) + goto fail; + + ret = pl172_timing_prop(adev, np, "mpmc,read-access-delay", + MPMC_STATIC_WAIT_RD(cs), + MPMC_STATIC_WAIT_RD_MAX, 1); + if (ret) + goto fail; + + ret = pl172_timing_prop(adev, np, "mpmc,page-mode-read-delay", + MPMC_STATIC_WAIT_PAGE(cs), + MPMC_STATIC_WAIT_PAGE_MAX, 1); + if (ret) + goto fail; + + ret = pl172_timing_prop(adev, np, "mpmc,write-access-delay", + MPMC_STATIC_WAIT_WR(cs), + MPMC_STATIC_WAIT_WR_MAX, 2); + if (ret) + goto fail; + + ret = pl172_timing_prop(adev, np, "mpmc,turn-round-delay", + MPMC_STATIC_WAIT_TURN(cs), + MPMC_STATIC_WAIT_TURN_MAX, 1); + if (ret) + goto fail; + + return 0; +fail: + dev_err(&adev->dev, "failed to configure cs%u\n", cs); + return ret; +} + +static int pl172_parse_cs_config(struct amba_device *adev, + struct device_node *np) +{ + u32 cs; + + if (!of_property_read_u32(np, "mpmc,cs", &cs)) { + if (cs >= PL172_MAX_CS) { + dev_err(&adev->dev, "cs%u invalid\n", cs); + return -EINVAL; + } + + return pl172_setup_static(adev, np, cs); + } + + dev_err(&adev->dev, "cs property required\n"); + + return -EINVAL; +} + +static const char * const pl172_revisions[] = {"r1", "r2", "r2p3", "r2p4"}; + +static int pl172_probe(struct amba_device *adev, const struct amba_id *id) +{ + struct device_node *child_np, *np = adev->dev.of_node; + struct device *dev = &adev->dev; + static const char *rev = "?"; + struct pl172_data *pl172; + int ret; + + if (amba_part(adev) == 0x172) { + if (amba_rev(adev) < ARRAY_SIZE(pl172_revisions)) + rev = pl172_revisions[amba_rev(adev)]; + } + + dev_info(dev, "ARM PL%x revision %s\n", amba_part(adev), rev); + + pl172 = devm_kzalloc(dev, sizeof(*pl172), GFP_KERNEL); + if (!pl172) + return -ENOMEM; + + pl172->clk = devm_clk_get(dev, "mpmcclk"); + if (IS_ERR(pl172->clk)) { + dev_err(dev, "no mpmcclk provided clock\n"); + return PTR_ERR(pl172->clk); + } + + ret = clk_prepare_enable(pl172->clk); + if (ret) { + dev_err(dev, "unable to mpmcclk enable clock\n"); + return ret; + } + + pl172->rate = clk_get_rate(pl172->clk) / MSEC_PER_SEC; + if (!pl172->rate) { + dev_err(dev, "unable to get mpmcclk clock rate\n"); + ret = -EINVAL; + goto err_clk_enable; + } + + ret = amba_request_regions(adev, NULL); + if (ret) { + dev_err(dev, "unable to request AMBA regions\n"); + goto err_clk_enable; + } + + pl172->base = devm_ioremap(dev, adev->res.start, + resource_size(&adev->res)); + if (!pl172->base) { + dev_err(dev, "ioremap failed\n"); + ret = -ENOMEM; + goto err_no_ioremap; + } + + amba_set_drvdata(adev, pl172); + + /* + * Loop through each child node, which represent a chip select, and + * configure parameters and timing. If successful; populate devices + * under that node. + */ + for_each_available_child_of_node(np, child_np) { + ret = pl172_parse_cs_config(adev, child_np); + if (ret) + continue; + + of_platform_populate(child_np, of_default_bus_match_table, + NULL, dev); + } + + return 0; + +err_no_ioremap: + amba_release_regions(adev); +err_clk_enable: + clk_disable_unprepare(pl172->clk); + return ret; +} + +static int pl172_remove(struct amba_device *adev) +{ + struct pl172_data *pl172 = amba_get_drvdata(adev); + + clk_disable_unprepare(pl172->clk); + amba_release_regions(adev); + + return 0; +} + +static struct amba_id pl172_ids[] = { + { + .id = 0x07341172, + .mask = 0xffffffff, + }, + { 0, 0 }, +}; +MODULE_DEVICE_TABLE(amba, pl172_ids); + +static struct amba_driver pl172_driver = { + .drv = { + .name = "memory-pl172", + }, + .probe = pl172_probe, + .remove = pl172_remove, + .id_table = pl172_ids, +}; +module_amba_driver(pl172_driver); + +MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>"); +MODULE_DESCRIPTION("PL172 Memory Controller Driver"); +MODULE_LICENSE("GPL v2"); -- 1.8.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 1/2] memory: add ARM PL172 MultiPort Memory Controller driver @ 2015-04-28 17:24 ` Joachim Eastwood 0 siblings, 0 replies; 12+ messages in thread From: Joachim Eastwood @ 2015-04-28 17:24 UTC (permalink / raw) To: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, arnd-r2nGTMty4D4, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Cc: linux-lFZ/pmaqli7XmaaqVzeoHQ, will.deacon-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, grant.likely-QSEj5FYQhm4dnm+yROfE0A, Joachim Eastwood Signed-off-by: Joachim Eastwood <manabian-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> --- drivers/memory/Kconfig | 8 ++ drivers/memory/Makefile | 1 + drivers/memory/pl172.c | 302 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 311 insertions(+) create mode 100644 drivers/memory/pl172.c diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 868036f70f8f..f69a8842ec69 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -7,6 +7,14 @@ menuconfig MEMORY if MEMORY +config ARM_PL172_MPMC + tristate "ARM PL172 MPMC driver" + depends on ARM_AMBA && OF + help + This selects the ARM PrimeCell PL172 MultiPort Memory Controller. + If you have an embedded system with an AMBA bus and a PL172 + controller, say Y or M here. + config ATMEL_SDRAMC bool "Atmel (Multi-port DDR-)SDRAM Controller" default y diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index b670441e3cdf..1c46af501610 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -5,6 +5,7 @@ ifeq ($(CONFIG_DDR),y) obj-$(CONFIG_OF) += of_memory.o endif +obj-$(CONFIG_ARM_PL172_MPMC) += pl172.o obj-$(CONFIG_ATMEL_SDRAMC) += atmel-sdramc.o obj-$(CONFIG_TI_AEMIF) += ti-aemif.o obj-$(CONFIG_TI_EMIF) += emif.o diff --git a/drivers/memory/pl172.c b/drivers/memory/pl172.c new file mode 100644 index 000000000000..552f92da9369 --- /dev/null +++ b/drivers/memory/pl172.c @@ -0,0 +1,302 @@ +/* + * Memory controller driver for ARM PrimeCell PL172 + * PrimeCell MultiPort Memory Controller (PL172) + * + * Copyright (C) 2015 Joachim Eastwood <manabian-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> + * + * Based on: + * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/amba/bus.h> +#include <linux/clk.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/time.h> + +#define MPMC_STATIC_CFG(n) (0x200 + 0x20 * n) +#define MPMC_STATIC_CFG_MW_8BIT 0x0 +#define MPMC_STATIC_CFG_MW_16BIT 0x1 +#define MPMC_STATIC_CFG_MW_32BIT 0x2 +#define MPMC_STATIC_CFG_PM BIT(3) +#define MPMC_STATIC_CFG_PC BIT(6) +#define MPMC_STATIC_CFG_PB BIT(7) +#define MPMC_STATIC_CFG_EW BIT(8) +#define MPMC_STATIC_CFG_B BIT(19) +#define MPMC_STATIC_CFG_P BIT(20) +#define MPMC_STATIC_WAIT_WEN(n) (0x204 + 0x20 * n) +#define MPMC_STATIC_WAIT_WEN_MAX 0x0f +#define MPMC_STATIC_WAIT_OEN(n) (0x208 + 0x20 * n) +#define MPMC_STATIC_WAIT_OEN_MAX 0x0f +#define MPMC_STATIC_WAIT_RD(n) (0x20c + 0x20 * n) +#define MPMC_STATIC_WAIT_RD_MAX 0x1f +#define MPMC_STATIC_WAIT_PAGE(n) (0x210 + 0x20 * n) +#define MPMC_STATIC_WAIT_PAGE_MAX 0x1f +#define MPMC_STATIC_WAIT_WR(n) (0x214 + 0x20 * n) +#define MPMC_STATIC_WAIT_WR_MAX 0x1f +#define MPMC_STATIC_WAIT_TURN(n) (0x218 + 0x20 * n) +#define MPMC_STATIC_WAIT_TURN_MAX 0x0f + +/* Maximum number of static chip selects */ +#define PL172_MAX_CS 4 + +struct pl172_data { + void __iomem *base; + unsigned long rate; + struct clk *clk; +}; + +static int pl172_timing_prop(struct amba_device *adev, + const struct device_node *np, const char *name, + u32 reg_offset, u32 max, int start) +{ + struct pl172_data *pl172 = amba_get_drvdata(adev); + int cycles; + u32 val; + + if (!of_property_read_u32(np, name, &val)) { + cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; + if (cycles < 0) { + cycles = 0; + } else if (cycles > max) { + dev_err(&adev->dev, "%s timing too tight\n", name); + return -EINVAL; + } + + writel(cycles, pl172->base + reg_offset); + } + + dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start + + readl(pl172->base + reg_offset)); + + return 0; +} + +static int pl172_setup_static(struct amba_device *adev, + struct device_node *np, u32 cs) +{ + struct pl172_data *pl172 = amba_get_drvdata(adev); + u32 cfg; + int ret; + + /* MPMC static memory configuration */ + if (!of_property_read_u32(np, "mpmc,memory-width", &cfg)) { + if (cfg == 8) { + cfg = MPMC_STATIC_CFG_MW_8BIT; + } else if (cfg == 16) { + cfg = MPMC_STATIC_CFG_MW_16BIT; + } else if (cfg == 32) { + cfg = MPMC_STATIC_CFG_MW_32BIT; + } else { + dev_err(&adev->dev, "invalid memory width cs%u\n", cs); + return -EINVAL; + } + } else { + dev_err(&adev->dev, "memory-width property required\n"); + return -EINVAL; + } + + if (of_property_read_bool(np, "mpmc,async-page-mode")) + cfg |= MPMC_STATIC_CFG_PM; + + if (of_property_read_bool(np, "mpmc,cs-active-high")) + cfg |= MPMC_STATIC_CFG_PC; + + if (of_property_read_bool(np, "mpmc,byte-lane-low")) + cfg |= MPMC_STATIC_CFG_PB; + + if (of_property_read_bool(np, "mpmc,extended-wait")) + cfg |= MPMC_STATIC_CFG_EW; + + if (of_property_read_bool(np, "mpmc,buffer-enable")) + cfg |= MPMC_STATIC_CFG_B; + + if (of_property_read_bool(np, "mpmc,write-protect")) + cfg |= MPMC_STATIC_CFG_P; + + writel(cfg, pl172->base + MPMC_STATIC_CFG(cs)); + dev_dbg(&adev->dev, "mpmc static config cs%u: 0x%08x\n", cs, cfg); + + /* MPMC static memory timing */ + ret = pl172_timing_prop(adev, np, "mpmc,write-enable-delay", + MPMC_STATIC_WAIT_WEN(cs), + MPMC_STATIC_WAIT_WEN_MAX, 1); + if (ret) + goto fail; + + ret = pl172_timing_prop(adev, np, "mpmc,output-enable-delay", + MPMC_STATIC_WAIT_OEN(cs), + MPMC_STATIC_WAIT_OEN_MAX, 0); + if (ret) + goto fail; + + ret = pl172_timing_prop(adev, np, "mpmc,read-access-delay", + MPMC_STATIC_WAIT_RD(cs), + MPMC_STATIC_WAIT_RD_MAX, 1); + if (ret) + goto fail; + + ret = pl172_timing_prop(adev, np, "mpmc,page-mode-read-delay", + MPMC_STATIC_WAIT_PAGE(cs), + MPMC_STATIC_WAIT_PAGE_MAX, 1); + if (ret) + goto fail; + + ret = pl172_timing_prop(adev, np, "mpmc,write-access-delay", + MPMC_STATIC_WAIT_WR(cs), + MPMC_STATIC_WAIT_WR_MAX, 2); + if (ret) + goto fail; + + ret = pl172_timing_prop(adev, np, "mpmc,turn-round-delay", + MPMC_STATIC_WAIT_TURN(cs), + MPMC_STATIC_WAIT_TURN_MAX, 1); + if (ret) + goto fail; + + return 0; +fail: + dev_err(&adev->dev, "failed to configure cs%u\n", cs); + return ret; +} + +static int pl172_parse_cs_config(struct amba_device *adev, + struct device_node *np) +{ + u32 cs; + + if (!of_property_read_u32(np, "mpmc,cs", &cs)) { + if (cs >= PL172_MAX_CS) { + dev_err(&adev->dev, "cs%u invalid\n", cs); + return -EINVAL; + } + + return pl172_setup_static(adev, np, cs); + } + + dev_err(&adev->dev, "cs property required\n"); + + return -EINVAL; +} + +static const char * const pl172_revisions[] = {"r1", "r2", "r2p3", "r2p4"}; + +static int pl172_probe(struct amba_device *adev, const struct amba_id *id) +{ + struct device_node *child_np, *np = adev->dev.of_node; + struct device *dev = &adev->dev; + static const char *rev = "?"; + struct pl172_data *pl172; + int ret; + + if (amba_part(adev) == 0x172) { + if (amba_rev(adev) < ARRAY_SIZE(pl172_revisions)) + rev = pl172_revisions[amba_rev(adev)]; + } + + dev_info(dev, "ARM PL%x revision %s\n", amba_part(adev), rev); + + pl172 = devm_kzalloc(dev, sizeof(*pl172), GFP_KERNEL); + if (!pl172) + return -ENOMEM; + + pl172->clk = devm_clk_get(dev, "mpmcclk"); + if (IS_ERR(pl172->clk)) { + dev_err(dev, "no mpmcclk provided clock\n"); + return PTR_ERR(pl172->clk); + } + + ret = clk_prepare_enable(pl172->clk); + if (ret) { + dev_err(dev, "unable to mpmcclk enable clock\n"); + return ret; + } + + pl172->rate = clk_get_rate(pl172->clk) / MSEC_PER_SEC; + if (!pl172->rate) { + dev_err(dev, "unable to get mpmcclk clock rate\n"); + ret = -EINVAL; + goto err_clk_enable; + } + + ret = amba_request_regions(adev, NULL); + if (ret) { + dev_err(dev, "unable to request AMBA regions\n"); + goto err_clk_enable; + } + + pl172->base = devm_ioremap(dev, adev->res.start, + resource_size(&adev->res)); + if (!pl172->base) { + dev_err(dev, "ioremap failed\n"); + ret = -ENOMEM; + goto err_no_ioremap; + } + + amba_set_drvdata(adev, pl172); + + /* + * Loop through each child node, which represent a chip select, and + * configure parameters and timing. If successful; populate devices + * under that node. + */ + for_each_available_child_of_node(np, child_np) { + ret = pl172_parse_cs_config(adev, child_np); + if (ret) + continue; + + of_platform_populate(child_np, of_default_bus_match_table, + NULL, dev); + } + + return 0; + +err_no_ioremap: + amba_release_regions(adev); +err_clk_enable: + clk_disable_unprepare(pl172->clk); + return ret; +} + +static int pl172_remove(struct amba_device *adev) +{ + struct pl172_data *pl172 = amba_get_drvdata(adev); + + clk_disable_unprepare(pl172->clk); + amba_release_regions(adev); + + return 0; +} + +static struct amba_id pl172_ids[] = { + { + .id = 0x07341172, + .mask = 0xffffffff, + }, + { 0, 0 }, +}; +MODULE_DEVICE_TABLE(amba, pl172_ids); + +static struct amba_driver pl172_driver = { + .drv = { + .name = "memory-pl172", + }, + .probe = pl172_probe, + .remove = pl172_remove, + .id_table = pl172_ids, +}; +module_amba_driver(pl172_driver); + +MODULE_AUTHOR("Joachim Eastwood <manabian-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>"); +MODULE_DESCRIPTION("PL172 Memory Controller Driver"); +MODULE_LICENSE("GPL v2"); -- 1.8.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] doc: dt: add documentation for pl172 memory bindings @ 2015-04-28 17:24 ` Joachim Eastwood 0 siblings, 0 replies; 12+ messages in thread From: Joachim Eastwood @ 2015-04-28 17:24 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Joachim Eastwood <manabian@gmail.com> --- .../bindings/memory-controllers/arm,pl172.txt | 125 +++++++++++++++++++++ 1 file changed, 125 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt b/Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt new file mode 100644 index 000000000000..e6df32f9986d --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt @@ -0,0 +1,125 @@ +* Device tree bindings for ARM PL172 MultiPort Memory Controller + +Required properties: + +- compatible: "arm,pl172", "arm,primecell" + +- reg: Must contains offset/length value for controller. + +- #address-cells: Must be 2. The partition number has to be encoded in the + first address cell and it may accept values 0..N-1 + (N - total number of partitions). The second cell is the + offset into the partition. + +- #size-cells: Must be set to 1. + +- ranges: Must contain one or more chip select memory regions. + +- clocks: Must contain references to controller clocks. + +- clock-names: Must contain "mpmcclk" and "apb_pclk". + +- clock-ranges: Empty property indicating that child nodes can inherit + named clocks. Required only if clock tree data present + in device tree. + See clock-bindings.txt + +Child chip-select (cs) nodes contain the memory devices nodes connected to +such as NOR (e.g. cfi-flash) and NAND. + +Required child cs node properties: + +- #address-cells: Must be 2. + +- #size-cells: Must be 1. + +- ranges: Empty property indicating that child nodes can inherit + memory layout. + +- clock-ranges: Empty property indicating that child nodes can inherit + named clocks. Required only if clock tree data present + in device tree. + +- mpmc,cs: Chip select number. Indicates to the pl0172 driver + which chipselect is used for accessing the memory. + +- mpmc,memory-width: Width of the chip select memory. Must be equal to + either 8, 16 or 32. + +Optional child cs node config properties: + +- mpmc,async-page-mode: Enable asynchronous page mode. + +- mpmc,cs-active-high: Set chip select polarity to active high. + +- mpmc,byte-lane-low: Set byte lane state to low. + +- mpmc,extended-wait: Enable extended wait. + +- mpmc,buffer-enable: Enable write buffer. + +- mpmc,write-protect: Enable write protect. + +Optional child cs node timing properties: + +- mpmc,write-enable-delay: Delay from chip select assertion to write + enable (WE signal) in nano seconds. + +- mpmc,output-enable-delay: Delay from chip select assertion to output + enable (OE signal) in nano seconds. + +- mpmc,write-access-delay: Delay from chip select assertion to write + access in nano seconds. + +- mpmc,read-access-delay: Delay from chip select assertion to read + access in nano seconds. + +- mpmc,page-mode-read-delay: Delay for asynchronous page mode sequential + accesses in nano seconds. + +- mpmc,turn-round-delay: Delay between access to memory banks in nano + seconds. + +If any of the above timing parameters are absent, current parameter value will +be taken from the corresponding HW reg. + +Example for pl172 with nor flash on chip select 0 shown below. + +emc: memory-controller at 40005000 { + compatible = "arm,pl172", "arm,primecell"; + reg = <0x40005000 0x1000>; + clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; + clock-names = "mpmcclk", "apb_pclk"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x1c000000 0x1000000 + 1 0 0x1d000000 0x1000000 + 2 0 0x1e000000 0x1000000 + 3 0 0x1f000000 0x1000000>; + + cs0 { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + mpmc,cs = <0>; + mpmc,memory-width = <16>; + mpmc,byte-lane-low; + mpmc,write-enable-delay = <0>; + mpmc,output-enable-delay = <0>; + mpmc,read-enable-delay = <70>; + mpmc,page-mode-read-delay = <70>; + + flash at 0,0 { + compatible = "sst,sst39vf320", "cfi-flash"; + reg = <0 0 0x400000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition at 0 { + label = "data"; + reg = <0 0x400000>; + }; + }; + }; +}; -- 1.8.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] doc: dt: add documentation for pl172 memory bindings @ 2015-04-28 17:24 ` Joachim Eastwood 0 siblings, 0 replies; 12+ messages in thread From: Joachim Eastwood @ 2015-04-28 17:24 UTC (permalink / raw) To: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, arnd-r2nGTMty4D4, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Cc: linux-lFZ/pmaqli7XmaaqVzeoHQ, will.deacon-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, grant.likely-QSEj5FYQhm4dnm+yROfE0A, Joachim Eastwood Signed-off-by: Joachim Eastwood <manabian-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> --- .../bindings/memory-controllers/arm,pl172.txt | 125 +++++++++++++++++++++ 1 file changed, 125 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt b/Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt new file mode 100644 index 000000000000..e6df32f9986d --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt @@ -0,0 +1,125 @@ +* Device tree bindings for ARM PL172 MultiPort Memory Controller + +Required properties: + +- compatible: "arm,pl172", "arm,primecell" + +- reg: Must contains offset/length value for controller. + +- #address-cells: Must be 2. The partition number has to be encoded in the + first address cell and it may accept values 0..N-1 + (N - total number of partitions). The second cell is the + offset into the partition. + +- #size-cells: Must be set to 1. + +- ranges: Must contain one or more chip select memory regions. + +- clocks: Must contain references to controller clocks. + +- clock-names: Must contain "mpmcclk" and "apb_pclk". + +- clock-ranges: Empty property indicating that child nodes can inherit + named clocks. Required only if clock tree data present + in device tree. + See clock-bindings.txt + +Child chip-select (cs) nodes contain the memory devices nodes connected to +such as NOR (e.g. cfi-flash) and NAND. + +Required child cs node properties: + +- #address-cells: Must be 2. + +- #size-cells: Must be 1. + +- ranges: Empty property indicating that child nodes can inherit + memory layout. + +- clock-ranges: Empty property indicating that child nodes can inherit + named clocks. Required only if clock tree data present + in device tree. + +- mpmc,cs: Chip select number. Indicates to the pl0172 driver + which chipselect is used for accessing the memory. + +- mpmc,memory-width: Width of the chip select memory. Must be equal to + either 8, 16 or 32. + +Optional child cs node config properties: + +- mpmc,async-page-mode: Enable asynchronous page mode. + +- mpmc,cs-active-high: Set chip select polarity to active high. + +- mpmc,byte-lane-low: Set byte lane state to low. + +- mpmc,extended-wait: Enable extended wait. + +- mpmc,buffer-enable: Enable write buffer. + +- mpmc,write-protect: Enable write protect. + +Optional child cs node timing properties: + +- mpmc,write-enable-delay: Delay from chip select assertion to write + enable (WE signal) in nano seconds. + +- mpmc,output-enable-delay: Delay from chip select assertion to output + enable (OE signal) in nano seconds. + +- mpmc,write-access-delay: Delay from chip select assertion to write + access in nano seconds. + +- mpmc,read-access-delay: Delay from chip select assertion to read + access in nano seconds. + +- mpmc,page-mode-read-delay: Delay for asynchronous page mode sequential + accesses in nano seconds. + +- mpmc,turn-round-delay: Delay between access to memory banks in nano + seconds. + +If any of the above timing parameters are absent, current parameter value will +be taken from the corresponding HW reg. + +Example for pl172 with nor flash on chip select 0 shown below. + +emc: memory-controller@40005000 { + compatible = "arm,pl172", "arm,primecell"; + reg = <0x40005000 0x1000>; + clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; + clock-names = "mpmcclk", "apb_pclk"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x1c000000 0x1000000 + 1 0 0x1d000000 0x1000000 + 2 0 0x1e000000 0x1000000 + 3 0 0x1f000000 0x1000000>; + + cs0 { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + mpmc,cs = <0>; + mpmc,memory-width = <16>; + mpmc,byte-lane-low; + mpmc,write-enable-delay = <0>; + mpmc,output-enable-delay = <0>; + mpmc,read-enable-delay = <70>; + mpmc,page-mode-read-delay = <70>; + + flash@0,0 { + compatible = "sst,sst39vf320", "cfi-flash"; + reg = <0 0 0x400000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "data"; + reg = <0 0x400000>; + }; + }; + }; +}; -- 1.8.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] doc: dt: add documentation for pl172 memory bindings @ 2015-05-12 17:44 ` Joachim Eastwood 0 siblings, 0 replies; 12+ messages in thread From: Joachim Eastwood @ 2015-05-12 17:44 UTC (permalink / raw) To: linux-arm-kernel Hi DT maintainers, Do you have any comments on the bindings below? These bindings are based on bindings for "ti,davinci-aemif" found under memory-controllers/ti-aemif.txt regards, Joachim Eastwood On 28 April 2015 at 19:24, Joachim Eastwood <manabian@gmail.com> wrote: > Signed-off-by: Joachim Eastwood <manabian@gmail.com> > --- > .../bindings/memory-controllers/arm,pl172.txt | 125 +++++++++++++++++++++ > 1 file changed, 125 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt > > diff --git a/Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt b/Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt > new file mode 100644 > index 000000000000..e6df32f9986d > --- /dev/null > +++ b/Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt > @@ -0,0 +1,125 @@ > +* Device tree bindings for ARM PL172 MultiPort Memory Controller > + > +Required properties: > + > +- compatible: "arm,pl172", "arm,primecell" > + > +- reg: Must contains offset/length value for controller. > + > +- #address-cells: Must be 2. The partition number has to be encoded in the > + first address cell and it may accept values 0..N-1 > + (N - total number of partitions). The second cell is the > + offset into the partition. > + > +- #size-cells: Must be set to 1. > + > +- ranges: Must contain one or more chip select memory regions. > + > +- clocks: Must contain references to controller clocks. > + > +- clock-names: Must contain "mpmcclk" and "apb_pclk". > + > +- clock-ranges: Empty property indicating that child nodes can inherit > + named clocks. Required only if clock tree data present > + in device tree. > + See clock-bindings.txt > + > +Child chip-select (cs) nodes contain the memory devices nodes connected to > +such as NOR (e.g. cfi-flash) and NAND. > + > +Required child cs node properties: > + > +- #address-cells: Must be 2. > + > +- #size-cells: Must be 1. > + > +- ranges: Empty property indicating that child nodes can inherit > + memory layout. > + > +- clock-ranges: Empty property indicating that child nodes can inherit > + named clocks. Required only if clock tree data present > + in device tree. > + > +- mpmc,cs: Chip select number. Indicates to the pl0172 driver > + which chipselect is used for accessing the memory. > + > +- mpmc,memory-width: Width of the chip select memory. Must be equal to > + either 8, 16 or 32. > + > +Optional child cs node config properties: > + > +- mpmc,async-page-mode: Enable asynchronous page mode. > + > +- mpmc,cs-active-high: Set chip select polarity to active high. > + > +- mpmc,byte-lane-low: Set byte lane state to low. > + > +- mpmc,extended-wait: Enable extended wait. > + > +- mpmc,buffer-enable: Enable write buffer. > + > +- mpmc,write-protect: Enable write protect. > + > +Optional child cs node timing properties: > + > +- mpmc,write-enable-delay: Delay from chip select assertion to write > + enable (WE signal) in nano seconds. > + > +- mpmc,output-enable-delay: Delay from chip select assertion to output > + enable (OE signal) in nano seconds. > + > +- mpmc,write-access-delay: Delay from chip select assertion to write > + access in nano seconds. > + > +- mpmc,read-access-delay: Delay from chip select assertion to read > + access in nano seconds. > + > +- mpmc,page-mode-read-delay: Delay for asynchronous page mode sequential > + accesses in nano seconds. > + > +- mpmc,turn-round-delay: Delay between access to memory banks in nano > + seconds. > + > +If any of the above timing parameters are absent, current parameter value will > +be taken from the corresponding HW reg. > + > +Example for pl172 with nor flash on chip select 0 shown below. > + > +emc: memory-controller at 40005000 { > + compatible = "arm,pl172", "arm,primecell"; > + reg = <0x40005000 0x1000>; > + clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; > + clock-names = "mpmcclk", "apb_pclk"; > + #address-cells = <2>; > + #size-cells = <1>; > + ranges = <0 0 0x1c000000 0x1000000 > + 1 0 0x1d000000 0x1000000 > + 2 0 0x1e000000 0x1000000 > + 3 0 0x1f000000 0x1000000>; > + > + cs0 { > + #address-cells = <2>; > + #size-cells = <1>; > + ranges; > + > + mpmc,cs = <0>; > + mpmc,memory-width = <16>; > + mpmc,byte-lane-low; > + mpmc,write-enable-delay = <0>; > + mpmc,output-enable-delay = <0>; > + mpmc,read-enable-delay = <70>; > + mpmc,page-mode-read-delay = <70>; > + > + flash at 0,0 { > + compatible = "sst,sst39vf320", "cfi-flash"; > + reg = <0 0 0x400000>; > + bank-width = <2>; > + #address-cells = <1>; > + #size-cells = <1>; > + partition at 0 { > + label = "data"; > + reg = <0 0x400000>; > + }; > + }; > + }; > +}; > -- > 1.8.0 > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] doc: dt: add documentation for pl172 memory bindings @ 2015-05-12 17:44 ` Joachim Eastwood 0 siblings, 0 replies; 12+ messages in thread From: Joachim Eastwood @ 2015-05-12 17:44 UTC (permalink / raw) To: Grant Likely, Rob Herring Cc: Russell King - ARM Linux, Arnd Bergmann, Greg Kroah-Hartman, Will Deacon, devicetree-u79uwXL29TY76Z2rM5mHXA, Joachim Eastwood, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org Hi DT maintainers, Do you have any comments on the bindings below? These bindings are based on bindings for "ti,davinci-aemif" found under memory-controllers/ti-aemif.txt regards, Joachim Eastwood On 28 April 2015 at 19:24, Joachim Eastwood <manabian-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > Signed-off-by: Joachim Eastwood <manabian-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > --- > .../bindings/memory-controllers/arm,pl172.txt | 125 +++++++++++++++++++++ > 1 file changed, 125 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt > > diff --git a/Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt b/Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt > new file mode 100644 > index 000000000000..e6df32f9986d > --- /dev/null > +++ b/Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt > @@ -0,0 +1,125 @@ > +* Device tree bindings for ARM PL172 MultiPort Memory Controller > + > +Required properties: > + > +- compatible: "arm,pl172", "arm,primecell" > + > +- reg: Must contains offset/length value for controller. > + > +- #address-cells: Must be 2. The partition number has to be encoded in the > + first address cell and it may accept values 0..N-1 > + (N - total number of partitions). The second cell is the > + offset into the partition. > + > +- #size-cells: Must be set to 1. > + > +- ranges: Must contain one or more chip select memory regions. > + > +- clocks: Must contain references to controller clocks. > + > +- clock-names: Must contain "mpmcclk" and "apb_pclk". > + > +- clock-ranges: Empty property indicating that child nodes can inherit > + named clocks. Required only if clock tree data present > + in device tree. > + See clock-bindings.txt > + > +Child chip-select (cs) nodes contain the memory devices nodes connected to > +such as NOR (e.g. cfi-flash) and NAND. > + > +Required child cs node properties: > + > +- #address-cells: Must be 2. > + > +- #size-cells: Must be 1. > + > +- ranges: Empty property indicating that child nodes can inherit > + memory layout. > + > +- clock-ranges: Empty property indicating that child nodes can inherit > + named clocks. Required only if clock tree data present > + in device tree. > + > +- mpmc,cs: Chip select number. Indicates to the pl0172 driver > + which chipselect is used for accessing the memory. > + > +- mpmc,memory-width: Width of the chip select memory. Must be equal to > + either 8, 16 or 32. > + > +Optional child cs node config properties: > + > +- mpmc,async-page-mode: Enable asynchronous page mode. > + > +- mpmc,cs-active-high: Set chip select polarity to active high. > + > +- mpmc,byte-lane-low: Set byte lane state to low. > + > +- mpmc,extended-wait: Enable extended wait. > + > +- mpmc,buffer-enable: Enable write buffer. > + > +- mpmc,write-protect: Enable write protect. > + > +Optional child cs node timing properties: > + > +- mpmc,write-enable-delay: Delay from chip select assertion to write > + enable (WE signal) in nano seconds. > + > +- mpmc,output-enable-delay: Delay from chip select assertion to output > + enable (OE signal) in nano seconds. > + > +- mpmc,write-access-delay: Delay from chip select assertion to write > + access in nano seconds. > + > +- mpmc,read-access-delay: Delay from chip select assertion to read > + access in nano seconds. > + > +- mpmc,page-mode-read-delay: Delay for asynchronous page mode sequential > + accesses in nano seconds. > + > +- mpmc,turn-round-delay: Delay between access to memory banks in nano > + seconds. > + > +If any of the above timing parameters are absent, current parameter value will > +be taken from the corresponding HW reg. > + > +Example for pl172 with nor flash on chip select 0 shown below. > + > +emc: memory-controller@40005000 { > + compatible = "arm,pl172", "arm,primecell"; > + reg = <0x40005000 0x1000>; > + clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; > + clock-names = "mpmcclk", "apb_pclk"; > + #address-cells = <2>; > + #size-cells = <1>; > + ranges = <0 0 0x1c000000 0x1000000 > + 1 0 0x1d000000 0x1000000 > + 2 0 0x1e000000 0x1000000 > + 3 0 0x1f000000 0x1000000>; > + > + cs0 { > + #address-cells = <2>; > + #size-cells = <1>; > + ranges; > + > + mpmc,cs = <0>; > + mpmc,memory-width = <16>; > + mpmc,byte-lane-low; > + mpmc,write-enable-delay = <0>; > + mpmc,output-enable-delay = <0>; > + mpmc,read-enable-delay = <70>; > + mpmc,page-mode-read-delay = <70>; > + > + flash@0,0 { > + compatible = "sst,sst39vf320", "cfi-flash"; > + reg = <0 0 0x400000>; > + bank-width = <2>; > + #address-cells = <1>; > + #size-cells = <1>; > + partition@0 { > + label = "data"; > + reg = <0 0x400000>; > + }; > + }; > + }; > +}; > -- > 1.8.0 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 0/2] Add support for PL172 memory-controller @ 2015-04-28 17:36 ` Will Deacon 0 siblings, 0 replies; 12+ messages in thread From: Will Deacon @ 2015-04-28 17:36 UTC (permalink / raw) To: linux-arm-kernel Hi Joachim, On Tue, Apr 28, 2015 at 06:24:37PM +0100, Joachim Eastwood wrote: > This patch set adds support for setting up static memory devices on > a ARM PrimeCell MultiPort Memory Controller (PL172) from DT. Dynamic > memory (SDRAM) is not supported in this patch set. > > DT bindings for PL172 is based on the bindings for the TI AEMIF > memory controller. PL172 can be found on a number of NXP devices > like the LPC18xx family. > > Tested on Embedded Artists' LPC4357 Developer's Kit with NOR Flash > (SST39VF320) and 74LCV16374 (gpio-74x164) on MPMC. Please excuse my ignorance here, but is this memory controller used to manage the memory in use by the kernel? If so, how is it safe to reconfigure it dynamically at runtime? If not, then it might be worth describing some typical use-cases in the binding documentation to motivate the existence of this driver. Cheers, Will ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/2] Add support for PL172 memory-controller @ 2015-04-28 17:36 ` Will Deacon 0 siblings, 0 replies; 12+ messages in thread From: Will Deacon @ 2015-04-28 17:36 UTC (permalink / raw) To: Joachim Eastwood Cc: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org, arnd-r2nGTMty4D4@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org Hi Joachim, On Tue, Apr 28, 2015 at 06:24:37PM +0100, Joachim Eastwood wrote: > This patch set adds support for setting up static memory devices on > a ARM PrimeCell MultiPort Memory Controller (PL172) from DT. Dynamic > memory (SDRAM) is not supported in this patch set. > > DT bindings for PL172 is based on the bindings for the TI AEMIF > memory controller. PL172 can be found on a number of NXP devices > like the LPC18xx family. > > Tested on Embedded Artists' LPC4357 Developer's Kit with NOR Flash > (SST39VF320) and 74LCV16374 (gpio-74x164) on MPMC. Please excuse my ignorance here, but is this memory controller used to manage the memory in use by the kernel? If so, how is it safe to reconfigure it dynamically at runtime? If not, then it might be worth describing some typical use-cases in the binding documentation to motivate the existence of this driver. Cheers, Will -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 0/2] Add support for PL172 memory-controller @ 2015-04-28 17:57 ` Joachim Eastwood 0 siblings, 0 replies; 12+ messages in thread From: Joachim Eastwood @ 2015-04-28 17:57 UTC (permalink / raw) To: linux-arm-kernel On 28 April 2015 at 19:36, Will Deacon <will.deacon@arm.com> wrote: > Hi Joachim, > > On Tue, Apr 28, 2015 at 06:24:37PM +0100, Joachim Eastwood wrote: >> This patch set adds support for setting up static memory devices on >> a ARM PrimeCell MultiPort Memory Controller (PL172) from DT. Dynamic >> memory (SDRAM) is not supported in this patch set. >> >> DT bindings for PL172 is based on the bindings for the TI AEMIF >> memory controller. PL172 can be found on a number of NXP devices >> like the LPC18xx family. >> >> Tested on Embedded Artists' LPC4357 Developer's Kit with NOR Flash >> (SST39VF320) and 74LCV16374 (gpio-74x164) on MPMC. > > Please excuse my ignorance here, but is this memory controller used to > manage the memory in use by the kernel? If so, how is it safe to reconfigure > it dynamically at runtime? The driver is used to do a one-time configuration of static chip selects on driver probe using the parameters specified in DT. The device nodes under the MPMC node is only populated and then driver probed after the parameters has been setup. This how most of drivers under drivers/memory operates. >If not, then it might be worth describing > some typical use-cases in the binding documentation to motivate the > existence of this driver. The typical use case is Flash memory (NAND and NOR) configuration and timing setup but you could configure any kind of static memory devices on the bus. But as described above this only happens at driver probe time. Hope this answer your question. regards, Joachim Eastwood ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/2] Add support for PL172 memory-controller @ 2015-04-28 17:57 ` Joachim Eastwood 0 siblings, 0 replies; 12+ messages in thread From: Joachim Eastwood @ 2015-04-28 17:57 UTC (permalink / raw) To: Will Deacon Cc: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org, arnd-r2nGTMty4D4@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org On 28 April 2015 at 19:36, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> wrote: > Hi Joachim, > > On Tue, Apr 28, 2015 at 06:24:37PM +0100, Joachim Eastwood wrote: >> This patch set adds support for setting up static memory devices on >> a ARM PrimeCell MultiPort Memory Controller (PL172) from DT. Dynamic >> memory (SDRAM) is not supported in this patch set. >> >> DT bindings for PL172 is based on the bindings for the TI AEMIF >> memory controller. PL172 can be found on a number of NXP devices >> like the LPC18xx family. >> >> Tested on Embedded Artists' LPC4357 Developer's Kit with NOR Flash >> (SST39VF320) and 74LCV16374 (gpio-74x164) on MPMC. > > Please excuse my ignorance here, but is this memory controller used to > manage the memory in use by the kernel? If so, how is it safe to reconfigure > it dynamically at runtime? The driver is used to do a one-time configuration of static chip selects on driver probe using the parameters specified in DT. The device nodes under the MPMC node is only populated and then driver probed after the parameters has been setup. This how most of drivers under drivers/memory operates. >If not, then it might be worth describing > some typical use-cases in the binding documentation to motivate the > existence of this driver. The typical use case is Flash memory (NAND and NOR) configuration and timing setup but you could configure any kind of static memory devices on the bus. But as described above this only happens at driver probe time. Hope this answer your question. regards, Joachim Eastwood -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2015-05-12 17:44 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-04-28 17:24 [PATCH 0/2] Add support for PL172 memory-controller Joachim Eastwood 2015-04-28 17:24 ` Joachim Eastwood 2015-04-28 17:24 ` [PATCH 1/2] memory: add ARM PL172 MultiPort Memory Controller driver Joachim Eastwood 2015-04-28 17:24 ` Joachim Eastwood 2015-04-28 17:24 ` [PATCH 2/2] doc: dt: add documentation for pl172 memory bindings Joachim Eastwood 2015-04-28 17:24 ` Joachim Eastwood 2015-05-12 17:44 ` Joachim Eastwood 2015-05-12 17:44 ` Joachim Eastwood 2015-04-28 17:36 ` [PATCH 0/2] Add support for PL172 memory-controller Will Deacon 2015-04-28 17:36 ` Will Deacon 2015-04-28 17:57 ` Joachim Eastwood 2015-04-28 17:57 ` Joachim Eastwood
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