Re: [Xenomai] Ipipe-core patched kernel fails to start when certain platform drivers are enabled

[Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org>]

On Fri, May 01, 2015 at 10:20:42AM -0400, Lennart Sorensen wrote:
> On Thu, Apr 30, 2015 at 11:34:04PM +0200, Gilles Chanteperdrix wrote:
> > I had tested architected timers on omap5432, and I believe the
> > counter frequency was something like 5 MHz, and a high latency, this
> > looks like a serious regression when omap4 had the global timer
> > running at 500 MHz and a 22ns latency in user-space (including the
> > time to jump to the kernel helper), which is better than the latency
> > I have on an atom N230 where reading the tsc is a dedicated
> > instruction (like architected timers actually).
> 
> Well the omap5 uses the A15 architecture timer.  The omap4 does not
> since the A9 didn't have one.

The point is: the cortex A9 global timer runs at half the processor
frequency, that is 500 MHz for a 1GHz processor: that gives a much
better resolution than a timer with a frequency lower than 10 MHz
you get with a cortex A15. So since the cortex A15 is newer than the
cortex A9, it could be expected to do better or at least be
equivalent, rather than do much worse.

> 
> Now they do have lots of other timers in the chip that can be programmed.
> I wonder if that could be used to make something much better.
> 
> I am pretty sure the omap5432 uses 6.144 MHz just like the am572x was
> supposed to (if it wasn't for the errata that makes it 6.147541
> MHz instead).

Yes, 5MHZ, 6 MHZ, that is the same bad order of magnitude.

> 
> Looking at the manual for the am572x it looks like the general purpose
> timers are only 32 bit and can run at either 32.768 KHz or system clock
> (usually 20 MHz).  That's not much help.

Once again: Xenomai extends 32 bits counter to 64 bits in software.
So, a 32 bits counter running at 20 MHz is still better than the
architected timer running at 6MHz. 6 MHz is so low that by reading
twice the counter in less than 166ns (which is really really doable
on these processors), you could get twice the same value. On cortex
A9, I could read the counter twice in userspace in 22ns, and get
different values. On cortex A9, anything lower than 50 MHz would
not have been sufficient for user-space.

-- 
					    Gilles.