From: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
Alexandre Courbot
<gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Paul Walmsley <pwalmsley-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH 1/3] soc/tegra: fuse: Add spare bit offset for Tegra114
Date: Mon, 4 May 2015 17:07:58 +0200 [thread overview]
Message-ID: <20150504150756.GA26419@ulmo.nvidia.com> (raw)
In-Reply-To: <1430750923-23682-1-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
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On Mon, May 04, 2015 at 04:48:41PM +0200, Thierry Reding wrote:
> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> The offset of the first spare bit register on Tegra114 is 0x280.
>
> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> drivers/soc/tegra/fuse/fuse-tegra30.c | 1 +
> 1 file changed, 1 insertion(+)
I just realized that all these offsets are offset by 0x100 because they
use the generic fuse access operation. Will update the series to reflect
that.
Thierry
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prev parent reply other threads:[~2015-05-04 15:07 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-04 14:48 [PATCH 1/3] soc/tegra: fuse: Add spare bit offset for Tegra114 Thierry Reding
[not found] ` <1430750923-23682-1-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-05-04 14:48 ` [PATCH 2/3] soc/tegra: fuse: Add spare bit offset for Tegra124 Thierry Reding
2015-05-04 14:48 ` [PATCH 3/3] soc/tegra: fuse: Add spare bit offset for Tegra210 Thierry Reding
2015-05-04 15:07 ` Thierry Reding [this message]
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