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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Damien Lespiau <damien.lespiau@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 5/8] drm/i915/skl: Make the Misc I/O power well part of the PLLS domain
Date: Tue, 5 May 2015 21:55:31 +0300	[thread overview]
Message-ID: <20150505185531.GM18908@intel.com> (raw)
In-Reply-To: <1430408363-20905-6-git-send-email-damien.lespiau@intel.com>

On Thu, Apr 30, 2015 at 04:39:20PM +0100, Damien Lespiau wrote:
> The specs tell us to ungate PG1 and Misc I/O at display init. We'll use
> the PLLS power domain to ensure those two power wells are up.
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Yep, spec does say that.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 6188e94..5b0bce5 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -309,6 +309,7 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
>  	BIT(POWER_DOMAIN_INIT))
>  #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS (		\
>  	SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS |		\
> +	BIT(POWER_DOMAIN_PLLS) |			\
>  	BIT(POWER_DOMAIN_INIT))
>  #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (		\
>  	(POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS |	\
> -- 
> 2.1.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2015-05-05 18:55 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-30 15:39 [PATCH 0/8] SKL suspend/resume Damien Lespiau
2015-04-30 15:39 ` [PATCH 1/8] drm/i915/skl: Add the INIT power domain to the MISC I/O power well Damien Lespiau
2015-05-05 18:54   ` Ville Syrjälä
2015-04-30 15:39 ` [PATCH 2/8] drm/i915/skl: Fix the CTRL typo in the DPLL_CRTL1 defines Damien Lespiau
2015-04-30 15:39 ` [PATCH 3/8] drm/i915: Re-order the PCU opcodes Damien Lespiau
2015-04-30 15:39 ` [PATCH 4/8] drm/i915: Merge the GEN9 memory latency PCU opcode with its friends Damien Lespiau
2015-05-05 18:54   ` Ville Syrjälä
2015-04-30 15:39 ` [PATCH 5/8] drm/i915/skl: Make the Misc I/O power well part of the PLLS domain Damien Lespiau
2015-05-05 18:55   ` Ville Syrjälä [this message]
2015-04-30 15:39 ` [PATCH 6/8] drm/i915/skl: Deinit/init the display at suspend/resume Damien Lespiau
2015-05-05 18:56   ` Ville Syrjälä
2015-05-06 11:10     ` Ville Syrjälä
2015-05-06 10:52   ` Daniel Vetter
2015-04-30 15:39 ` [PATCH 7/8] drm/i915/skl: Change CDCLK behind PCU's back Damien Lespiau
2015-05-06 10:53   ` Daniel Vetter
2015-05-06 10:58     ` Damien Lespiau
2015-04-30 15:39 ` [PATCH 8/8] drm/i915/skl: gen6+ platforms support runtime PM Damien Lespiau
2015-05-02  8:20   ` shuang.he
2015-05-05 18:56   ` Ville Syrjälä
2015-05-06 10:54   ` Daniel Vetter
2015-05-06 10:55     ` Damien Lespiau

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