diff for duplicates of <20150506141816.GF22098@ulmo.nvidia.com> diff --git a/a/1.txt b/N1/1.txt index 688c402..a97f41a 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,11 +1,11 @@ On Mon, May 04, 2015 at 01:35:09PM -0700, Benson Leung wrote: -> On Mon, May 4, 2015 at 9:37 AM, Rhyland Klein <rklein@nvidia.com> wrote: -> > From: Bill Huang <bilhuang@nvidia.com> +> On Mon, May 4, 2015 at 9:37 AM, Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote: +> > From: Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > > > > New SoC's may have more then 3 MISC registers, so bump up the > > array size and use a #define to be more informative about the value. > > -> > Signed-off-by: Bill Huang <bilhuang@nvidia.com> +> > Signed-off-by: Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > > --- > > drivers/clk/tegra/clk.h | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/a/content_digest b/N1/content_digest index 848703f..84f8614 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,30 +1,31 @@ "ref\01430757460-9478-1-git-send-email-rklein@nvidia.com\0" "ref\01430757460-9478-7-git-send-email-rklein@nvidia.com\0" "ref\0CANLzEksajPjf1VH8Zn-1oXhgL8f-b7GuCBprExTP-w18WbCC4A@mail.gmail.com\0" - "From\0Thierry Reding <thierry.reding@gmail.com>\0" + "ref\0CANLzEksajPjf1VH8Zn-1oXhgL8f-b7GuCBprExTP-w18WbCC4A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org\0" + "From\0Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" "Subject\0Re: [PATCH v4 06/20] clk: tegra: pll-params: change misc_reg count from 3 -> 6\0" "Date\0Wed, 6 May 2015 16:18:17 +0200\0" - "To\0Benson Leung <bleung@chromium.org>\0" - "Cc\0Rhyland Klein <rklein@nvidia.com>" - Peter De Schrijver <pdeschrijver@nvidia.com> - Mike Turquette <mturquette@linaro.org> - Stephen Warren <swarren@wwwdotorg.org> - Stephen Boyd <sboyd@codeaurora.org> - Alexandre Courbot <gnurou@gmail.com> - linux-clk@vger.kernel.org - linux-tegra@vger.kernel.org - linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> - " Bill Huang <bilhuang@nvidia.com>\0" + "To\0Benson Leung <bleung-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>\0" + "Cc\0Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>" + Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> + Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> + Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> + Alexandre Courbot <gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> + linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + " Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" "\01:1\0" "b\0" "On Mon, May 04, 2015 at 01:35:09PM -0700, Benson Leung wrote:\n" - "> On Mon, May 4, 2015 at 9:37 AM, Rhyland Klein <rklein@nvidia.com> wrote:\n" - "> > From: Bill Huang <bilhuang@nvidia.com>\n" + "> On Mon, May 4, 2015 at 9:37 AM, Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:\n" + "> > From: Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" "> >\n" "> > New SoC's may have more then 3 MISC registers, so bump up the\n" "> > array size and use a #define to be more informative about the value.\n" "> >\n" - "> > Signed-off-by: Bill Huang <bilhuang@nvidia.com>\n" + "> > Signed-off-by: Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" "> > ---\n" "> > drivers/clk/tegra/clk.h | 4 +++-\n" "> > 1 file changed, 3 insertions(+), 1 deletion(-)\n" @@ -80,4 +81,4 @@ "=LhiZ\n" "-----END PGP SIGNATURE-----\n" -15fe2570b65b1cfd6846e7cb7ce4ab4369e944d3f82734f2baefab2e59f366f6 +68917804da6c313a0d40aa2449533778fded14db7df1bffb0599ab401dbb2848
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