diff for duplicates of <20150510104121.GF11057@lukather> diff --git a/a/1.txt b/N1/1.txt index 9c0bf4f..d156011 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -7,7 +7,7 @@ On Sun, May 10, 2015 at 12:16:21PM +0530, Vishnu Patekar wrote: > > I don't have a23 device, however, dts got compiled. > -> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com> +> Signed-off-by: VishnuPatekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Once again, that patch does several unrelated things at once. @@ -105,7 +105,7 @@ It adds a new compatible to boards. > - #size-cells = <1>; > - ranges; > - -> - framebuffer at 0 { +> - framebuffer@0 { > - compatible = "allwinner,simple-framebuffer", > - "simple-framebuffer"; > - allwinner,pipeline = "de_be0-lcd0"; @@ -155,7 +155,7 @@ It updates a CPU enable method. > - clock-output-names = "osc32k"; > - }; > - -> - pll1: clk at 01c20000 { +> - pll1: clk@01c20000 { > - #clock-cells = <0>; > - compatible = "allwinner,sun8i-a23-pll1-clk"; > - reg = <0x01c20000 0x4>; @@ -170,7 +170,7 @@ It updates a CPU enable method. > clock-output-names = "pll5"; > }; > -> - pll6: clk at 01c20028 { +> - pll6: clk@01c20028 { > - #clock-cells = <1>; > - compatible = "allwinner,sun6i-a31-pll6-clk"; > - reg = <0x01c20028 0x4>; @@ -178,7 +178,7 @@ It updates a CPU enable method. > - clock-output-names = "pll6", "pll6x2"; > - }; > - -> - cpu: cpu_clk at 01c20050 { +> - cpu: cpu_clk@01c20050 { > - #clock-cells = <0>; > - compatible = "allwinner,sun4i-a10-cpu-clk"; > - reg = <0x01c20050 0x4>; @@ -193,14 +193,14 @@ It updates a CPU enable method. > - clock-output-names = "cpu"; > - }; > - -> axi: axi_clk at 01c20050 { +> axi: axi_clk@01c20050 { > #clock-cells = <0>; > compatible = "allwinner,sun8i-a23-axi-clk"; > @@ -168,22 +85,6 @@ > clock-output-names = "axi"; > }; > -> - ahb1: ahb1_clk at 01c20054 { +> - ahb1: ahb1_clk@01c20054 { > - #clock-cells = <0>; > - compatible = "allwinner,sun6i-a31-ahb1-clk"; > - reg = <0x01c20054 0x4>; @@ -208,7 +208,7 @@ It updates a CPU enable method. > - clock-output-names = "ahb1"; > - }; > - -> - apb1: apb1_clk at 01c20054 { +> - apb1: apb1_clk@01c20054 { > - #clock-cells = <0>; > - compatible = "allwinner,sun4i-a10-apb0-clk"; > - reg = <0x01c20054 0x4>; @@ -216,14 +216,14 @@ It updates a CPU enable method. > - clock-output-names = "apb1"; > - }; > - -> ahb1_gates: clk at 01c20060 { +> ahb1_gates: clk@01c20060 { > #clock-cells = <1>; > compatible = "allwinner,sun8i-a23-ahb1-gates-clk"; > @@ -228,36 +129,6 @@ > "apb2_uart3", "apb2_uart4"; > }; > -> - mmc0_clk: clk at 01c20088 { +> - mmc0_clk: clk@01c20088 { > - #clock-cells = <1>; > - compatible = "allwinner,sun4i-a10-mmc-clk"; > - reg = <0x01c20088 0x4>; @@ -233,7 +233,7 @@ It updates a CPU enable method. > - "mmc0_sample"; > - }; > - -> - mmc1_clk: clk at 01c2008c { +> - mmc1_clk: clk@01c2008c { > - #clock-cells = <1>; > - compatible = "allwinner,sun4i-a10-mmc-clk"; > - reg = <0x01c2008c 0x4>; @@ -243,7 +243,7 @@ It updates a CPU enable method. > - "mmc1_sample"; > - }; > - -> - mmc2_clk: clk at 01c20090 { +> - mmc2_clk: clk@01c20090 { > - #clock-cells = <1>; > - compatible = "allwinner,sun4i-a10-mmc-clk"; > - reg = <0x01c20090 0x4>; @@ -253,26 +253,26 @@ It updates a CPU enable method. > - "mmc2_sample"; > - }; > - -> mbus_clk: clk at 01c2015c { +> mbus_clk: clk@01c2015c { > #clock-cells = <0>; > compatible = "allwinner,sun8i-a23-mbus-clk"; > @@ -268,11 +139,6 @@ > }; > -> soc at 01c00000 { +> soc@01c00000 { > - compatible = "simple-bus"; > - #address-cells = <1>; > - #size-cells = <1>; > - ranges; > - -> dma: dma-controller at 01c02000 { +> dma: dma-controller@01c02000 { > compatible = "allwinner,sun8i-a23-dma"; > reg = <0x01c02000 0x1000>; > @@ -282,75 +148,12 @@ > #dma-cells = <1>; > }; > -> - mmc0: mmc at 01c0f000 { +> - mmc0: mmc@01c0f000 { > - compatible = "allwinner,sun5i-a13-mmc"; > - reg = <0x01c0f000 0x1000>; > - clocks = <&ahb1_gates 8>, @@ -291,7 +291,7 @@ It updates a CPU enable method. > - #size-cells = <0>; > - }; > - -> - mmc1: mmc at 01c10000 { +> - mmc1: mmc@01c10000 { > - compatible = "allwinner,sun5i-a13-mmc"; > - reg = <0x01c10000 0x1000>; > - clocks = <&ahb1_gates 9>, @@ -310,7 +310,7 @@ It updates a CPU enable method. > - #size-cells = <0>; > - }; > - -> - mmc2: mmc at 01c11000 { +> - mmc2: mmc@01c11000 { > - compatible = "allwinner,sun5i-a13-mmc"; > - reg = <0x01c11000 0x1000>; > - clocks = <&ahb1_gates 10>, @@ -329,7 +329,7 @@ It updates a CPU enable method. > - #size-cells = <0>; > - }; > - -> pio: pinctrl at 01c20800 { +> pio: pinctrl@01c20800 { > compatible = "allwinner,sun8i-a23-pinctrl"; > - reg = <0x01c20800 0x400>; > interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -343,52 +343,52 @@ It updates a CPU enable method. > - #gpio-cells = <3>; > + > -> uart0_pins_a: uart0 at 0 { +> uart0_pins_a: uart0@0 { > allwinner,pins = "PF2", "PF4"; > @@ -359,20 +162,6 @@ > allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > }; > -> - mmc0_pins_a: mmc0 at 0 { +> - mmc0_pins_a: mmc0@0 { > - allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; > - allwinner,function = "mmc0"; > - allwinner,drive = <SUN4I_PINCTRL_30_MA>; > - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > - }; > - -> - mmc1_pins_a: mmc1 at 0 { +> - mmc1_pins_a: mmc1@0 { > - allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5"; > - allwinner,function = "mmc1"; > - allwinner,drive = <SUN4I_PINCTRL_30_MA>; > - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > - }; > - -> i2c0_pins_a: i2c0 at 0 { +> i2c0_pins_a: i2c0@0 { > allwinner,pins = "PH2", "PH3"; > allwinner,function = "i2c0"; > @@ -395,38 +184,6 @@ > }; > }; > -> - ahb1_rst: reset at 01c202c0 { +> - ahb1_rst: reset@01c202c0 { > - #reset-cells = <1>; > - compatible = "allwinner,sun6i-a31-clock-reset"; > - reg = <0x01c202c0 0xc>; > - }; > - -> - apb1_rst: reset at 01c202d0 { +> - apb1_rst: reset@01c202d0 { > - #reset-cells = <1>; > - compatible = "allwinner,sun6i-a31-clock-reset"; > - reg = <0x01c202d0 0x4>; > - }; > - -> - apb2_rst: reset at 01c202d8 { +> - apb2_rst: reset@01c202d8 { > - #reset-cells = <1>; > - compatible = "allwinner,sun6i-a31-clock-reset"; > - reg = <0x01c202d8 0x4>; > - }; > - -> - timer at 01c20c00 { +> - timer@01c20c00 { > - compatible = "allwinner,sun4i-a10-timer"; > - reg = <0x01c20c00 0xa0>; > - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -396,20 +396,20 @@ It updates a CPU enable method. > - clocks = <&osc24M>; > - }; > - -> - wdt0: watchdog at 01c20ca0 { +> - wdt0: watchdog@01c20ca0 { > - compatible = "allwinner,sun6i-a31-wdt"; > - reg = <0x01c20ca0 0x20>; > - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; > - }; > - -> lradc: lradc at 01c22800 { +> lradc: lradc@01c22800 { > compatible = "allwinner,sun4i-a10-lradc-keys"; > reg = <0x01c22800 0x100>; > @@ -434,58 +191,6 @@ > status = "disabled"; > }; > -> - uart0: serial at 01c28000 { +> - uart0: serial@01c28000 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x01c28000 0x400>; > - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -422,7 +422,7 @@ It updates a CPU enable method. > - status = "disabled"; > - }; > - -> - uart1: serial at 01c28400 { +> - uart1: serial@01c28400 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x01c28400 0x400>; > - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -435,7 +435,7 @@ It updates a CPU enable method. > - status = "disabled"; > - }; > - -> - uart2: serial at 01c28800 { +> - uart2: serial@01c28800 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x01c28800 0x400>; > - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -448,7 +448,7 @@ It updates a CPU enable method. > - status = "disabled"; > - }; > - -> - uart3: serial at 01c28c00 { +> - uart3: serial@01c28c00 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x01c28c00 0x400>; > - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -461,7 +461,7 @@ It updates a CPU enable method. > - status = "disabled"; > - }; > - -> uart4: serial at 01c29000 { +> uart4: serial@01c29000 { > compatible = "snps,dw-apb-uart"; > reg = <0x01c29000 0x400>; > @@ -498,136 +203,5 @@ @@ -469,7 +469,7 @@ It updates a CPU enable method. > status = "disabled"; > }; > - -> - i2c0: i2c at 01c2ac00 { +> - i2c0: i2c@01c2ac00 { > - compatible = "allwinner,sun6i-a31-i2c"; > - reg = <0x01c2ac00 0x400>; > - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -480,7 +480,7 @@ It updates a CPU enable method. > - #size-cells = <0>; > - }; > - -> - i2c1: i2c at 01c2b000 { +> - i2c1: i2c@01c2b000 { > - compatible = "allwinner,sun6i-a31-i2c"; > - reg = <0x01c2b000 0x400>; > - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -491,7 +491,7 @@ It updates a CPU enable method. > - #size-cells = <0>; > - }; > - -> - i2c2: i2c at 01c2b400 { +> - i2c2: i2c@01c2b400 { > - compatible = "allwinner,sun6i-a31-i2c"; > - reg = <0x01c2b400 0x400>; > - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; @@ -502,7 +502,7 @@ It updates a CPU enable method. > - #size-cells = <0>; > - }; > - -> - gic: interrupt-controller at 01c81000 { +> - gic: interrupt-controller@01c81000 { > - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; > - reg = <0x01c81000 0x1000>, > - <0x01c82000 0x1000>, @@ -513,14 +513,14 @@ It updates a CPU enable method. > - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > - }; > - -> - rtc: rtc at 01f00000 { +> - rtc: rtc@01f00000 { > - compatible = "allwinner,sun6i-a31-rtc"; > - reg = <0x01f00000 0x54>; > - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > - }; > - -> - prcm at 01f01400 { +> - prcm@01f01400 { > - compatible = "allwinner,sun8i-a23-prcm"; > - reg = <0x01f01400 0x200>; > - @@ -564,12 +564,12 @@ It updates a CPU enable method. > - }; > - }; > - -> - cpucfg at 01f01c00 { +> - cpucfg@01f01c00 { > - compatible = "allwinner,sun8i-a23-cpuconfig"; > - reg = <0x01f01c00 0x300>; > - }; > - -> - r_uart: serial at 01f02800 { +> - r_uart: serial@01f02800 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x01f02800 0x400>; > - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; @@ -580,7 +580,7 @@ It updates a CPU enable method. > - status = "disabled"; > - }; > - -> - r_pio: pinctrl at 01f02c00 { +> - r_pio: pinctrl@01f02c00 { > - compatible = "allwinner,sun8i-a23-r-pinctrl"; > - reg = <0x01f02c00 0x400>; > - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -592,7 +592,7 @@ It updates a CPU enable method. > - #size-cells = <0>; > - #gpio-cells = <3>; > - -> - r_uart_pins_a: r_uart at 0 { +> - r_uart_pins_a: r_uart@0 { > - allwinner,pins = "PL2", "PL3"; > - allwinner,function = "s_uart"; > - allwinner,drive = <SUN4I_PINCTRL_10_MA>; @@ -610,7 +610,7 @@ It updates a CPU enable method. > +/* > + * Copyright 2014 Chen-Yu Tsai > + * -> + * Chen-Yu Tsai <wens@csie.org> +> + * Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual @@ -666,7 +666,7 @@ It updates a CPU enable method. > + #size-cells = <1>; > + ranges; > + -> + framebuffer at 0 { +> + framebuffer@0 { > + compatible = "allwinner,simple-framebuffer", > + "simple-framebuffer"; > + allwinner,pipeline = "de_be0-lcd0"; @@ -704,7 +704,7 @@ It updates a CPU enable method. > + clock-output-names = "osc32k"; > + }; > + -> + pll1: clk at 01c20000 { +> + pll1: clk@01c20000 { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-a23-pll1-clk"; > + reg = <0x01c20000 0x4>; @@ -712,7 +712,7 @@ It updates a CPU enable method. > + clock-output-names = "pll1"; > + }; > + -> + pll6: clk at 01c20028 { +> + pll6: clk@01c20028 { > + #clock-cells = <1>; > + compatible = "allwinner,sun6i-a31-pll6-clk"; > + reg = <0x01c20028 0x4>; @@ -720,7 +720,7 @@ It updates a CPU enable method. > + clock-output-names = "pll6", "pll6x2"; > + }; > + -> + cpu: cpu_clk at 01c20050 { +> + cpu: cpu_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-cpu-clk"; > + reg = <0x01c20050 0x4>; @@ -736,7 +736,7 @@ It updates a CPU enable method. > + }; > + > + -> + ahb1: ahb1_clk at 01c20054 { +> + ahb1: ahb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-ahb1-clk"; > + reg = <0x01c20054 0x4>; @@ -744,7 +744,7 @@ It updates a CPU enable method. > + clock-output-names = "ahb1"; > + }; > + -> + apb1: apb1_clk at 01c20054 { +> + apb1: apb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb0-clk"; > + reg = <0x01c20054 0x4>; @@ -752,7 +752,7 @@ It updates a CPU enable method. > + clock-output-names = "apb1"; > + }; > + -> + mmc0_clk: clk at 01c20088 { +> + mmc0_clk: clk@01c20088 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20088 0x4>; @@ -762,7 +762,7 @@ It updates a CPU enable method. > + "mmc0_sample"; > + }; > + -> + mmc1_clk: clk at 01c2008c { +> + mmc1_clk: clk@01c2008c { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c2008c 0x4>; @@ -772,7 +772,7 @@ It updates a CPU enable method. > + "mmc1_sample"; > + }; > + -> + mmc2_clk: clk at 01c20090 { +> + mmc2_clk: clk@01c20090 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20090 0x4>; @@ -784,14 +784,14 @@ It updates a CPU enable method. > + > + }; > + -> + soc at 01c00000 { +> + soc@01c00000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + -> + mmc0: mmc at 01c0f000 { +> + mmc0: mmc@01c0f000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c0f000 0x1000>; > + clocks = <&ahb1_gates 8>, @@ -810,7 +810,7 @@ It updates a CPU enable method. > + #size-cells = <0>; > + }; > + -> + mmc1: mmc at 01c10000 { +> + mmc1: mmc@01c10000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c10000 0x1000>; > + clocks = <&ahb1_gates 9>, @@ -829,7 +829,7 @@ It updates a CPU enable method. > + #size-cells = <0>; > + }; > + -> + mmc2: mmc at 01c11000 { +> + mmc2: mmc@01c11000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c11000 0x1000>; > + clocks = <&ahb1_gates 10>, @@ -848,7 +848,7 @@ It updates a CPU enable method. > + #size-cells = <0>; > + }; > + -> + pio: pinctrl at 01c20800 { +> + pio: pinctrl@01c20800 { > + reg = <0x01c20800 0x400>; > + clocks = <&apb1_gates 5>; > + gpio-controller; @@ -857,14 +857,14 @@ It updates a CPU enable method. > + #size-cells = <0>; > + #gpio-cells = <3>; > + -> + mmc0_pins_a: mmc0 at 0 { +> + mmc0_pins_a: mmc0@0 { > + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; > + allwinner,function = "mmc0"; > + allwinner,drive = <SUN4I_PINCTRL_30_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + mmc1_pins_a: mmc1 at 0 { +> + mmc1_pins_a: mmc1@0 { > + allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5"; > + allwinner,function = "mmc1"; > + allwinner,drive = <SUN4I_PINCTRL_30_MA>; @@ -872,25 +872,25 @@ It updates a CPU enable method. > + }; > + }; > + -> + ahb1_rst: reset at 01c202c0 { +> + ahb1_rst: reset@01c202c0 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-clock-reset"; > + reg = <0x01c202c0 0xc>; > + }; > + -> + apb1_rst: reset at 01c202d0 { +> + apb1_rst: reset@01c202d0 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-clock-reset"; > + reg = <0x01c202d0 0x4>; > + }; > + -> + apb2_rst: reset at 01c202d8 { +> + apb2_rst: reset@01c202d8 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-clock-reset"; > + reg = <0x01c202d8 0x4>; > + }; > + -> + timer at 01c20c00 { +> + timer@01c20c00 { > + compatible = "allwinner,sun4i-a10-timer"; > + reg = <0x01c20c00 0xa0>; > + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -898,13 +898,13 @@ It updates a CPU enable method. > + clocks = <&osc24M>; > + }; > + -> + wdt0: watchdog at 01c20ca0 { +> + wdt0: watchdog@01c20ca0 { > + compatible = "allwinner,sun6i-a31-wdt"; > + reg = <0x01c20ca0 0x20>; > + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; > + }; > + -> + uart0: serial at 01c28000 { +> + uart0: serial@01c28000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28000 0x400>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -917,7 +917,7 @@ It updates a CPU enable method. > + status = "disabled"; > + }; > + -> + uart1: serial at 01c28400 { +> + uart1: serial@01c28400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28400 0x400>; > + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -930,7 +930,7 @@ It updates a CPU enable method. > + status = "disabled"; > + }; > + -> + uart2: serial at 01c28800 { +> + uart2: serial@01c28800 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28800 0x400>; > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -943,7 +943,7 @@ It updates a CPU enable method. > + status = "disabled"; > + }; > + -> + uart3: serial at 01c28c00 { +> + uart3: serial@01c28c00 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28c00 0x400>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -956,7 +956,7 @@ It updates a CPU enable method. > + status = "disabled"; > + }; > + -> + i2c0: i2c at 01c2ac00 { +> + i2c0: i2c@01c2ac00 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2ac00 0x400>; > + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -967,7 +967,7 @@ It updates a CPU enable method. > + #size-cells = <0>; > + }; > + -> + i2c1: i2c at 01c2b000 { +> + i2c1: i2c@01c2b000 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2b000 0x400>; > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -978,7 +978,7 @@ It updates a CPU enable method. > + #size-cells = <0>; > + }; > + -> + i2c2: i2c at 01c2b400 { +> + i2c2: i2c@01c2b400 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2b400 0x400>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; @@ -989,7 +989,7 @@ It updates a CPU enable method. > + #size-cells = <0>; > + }; > + -> + gic: interrupt-controller at 01c81000 { +> + gic: interrupt-controller@01c81000 { > + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; > + reg = <0x01c81000 0x1000>, > + <0x01c82000 0x1000>, @@ -1000,14 +1000,14 @@ It updates a CPU enable method. > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + -> + rtc: rtc at 01f00000 { +> + rtc: rtc@01f00000 { > + compatible = "allwinner,sun6i-a31-rtc"; > + reg = <0x01f00000 0x54>; > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > + }; > + -> + prcm at 01f01400 { +> + prcm@01f01400 { > + compatible = "allwinner,sun8i-a23-prcm"; > + reg = <0x01f01400 0x200>; > + @@ -1051,12 +1051,12 @@ It updates a CPU enable method. > + }; > + }; > + -> + cpucfg at 01f01c00 { +> + cpucfg@01f01c00 { > + compatible = "allwinner,sun8i-a23-cpuconfig"; > + reg = <0x01f01c00 0x300>; > + }; > + -> + r_uart: serial at 01f02800 { +> + r_uart: serial@01f02800 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01f02800 0x400>; > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; @@ -1067,7 +1067,7 @@ It updates a CPU enable method. > + status = "disabled"; > + }; > + -> + r_pio: pinctrl at 01f02c00 { +> + r_pio: pinctrl@01f02c00 { > + compatible = "allwinner,sun8i-a23-r-pinctrl"; > + reg = <0x01f02c00 0x400>; > + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -1079,7 +1079,7 @@ It updates a CPU enable method. > + #size-cells = <0>; > + #gpio-cells = <3>; > + -> + r_uart_pins_a: r_uart at 0 { +> + r_uart_pins_a: r_uart@0 { > + allwinner,pins = "PL2", "PL3"; > + allwinner,function = "s_uart"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; @@ -1110,10 +1110,3 @@ Maxime Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --------------- next part -------------- -A non-text attachment was scrubbed... -Name: signature.asc -Type: application/pgp-signature -Size: 819 bytes -Desc: Digital signature -URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20150510/1821ffb1/attachment-0001.sig> diff --git a/a/content_digest b/N1/content_digest index fe1e546..62accf7 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,10 +1,22 @@ "ref\01431240383-12763-1-git-send-email-vishnupatekar0510@gmail.com\0" "ref\01431240383-12763-5-git-send-email-vishnupatekar0510@gmail.com\0" - "From\0maxime.ripard@free-electrons.com (Maxime Ripard)\0" - "Subject\0[PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi\0" + "ref\01431240383-12763-5-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" + "From\0Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>\0" + "Subject\0Re: [PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi\0" "Date\0Sun, 10 May 2015 12:41:21 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" - "\00:1\0" + "To\0Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" + "Cc\0emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org" + linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org + wens-jdAy2FN1RRM@public.gmane.org + jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org + arnd-r2nGTMty4D4@public.gmane.org + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org + " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "\01:1\0" "b\0" "Hi,\n" "\n" @@ -15,7 +27,7 @@ "> \n" "> I don't have a23 device, however, dts got compiled.\n" "> \n" - "> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>\n" + "> Signed-off-by: VishnuPatekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" "\n" "Once again, that patch does several unrelated things at once.\n" "\n" @@ -113,7 +125,7 @@ "> -\t\t#size-cells = <1>;\n" "> -\t\tranges;\n" "> -\n" - "> -\t\tframebuffer at 0 {\n" + "> -\t\tframebuffer@0 {\n" "> -\t\t\tcompatible = \"allwinner,simple-framebuffer\",\n" "> -\t\t\t\t \"simple-framebuffer\";\n" "> -\t\t\tallwinner,pipeline = \"de_be0-lcd0\";\n" @@ -163,7 +175,7 @@ "> -\t\t\tclock-output-names = \"osc32k\";\n" "> -\t\t};\n" "> -\n" - "> -\t\tpll1: clk at 01c20000 {\n" + "> -\t\tpll1: clk@01c20000 {\n" "> -\t\t\t#clock-cells = <0>;\n" "> -\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n" "> -\t\t\treg = <0x01c20000 0x4>;\n" @@ -178,7 +190,7 @@ "> \t\t\tclock-output-names = \"pll5\";\n" "> \t\t};\n" "> \n" - "> -\t\tpll6: clk at 01c20028 {\n" + "> -\t\tpll6: clk@01c20028 {\n" "> -\t\t\t#clock-cells = <1>;\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" "> -\t\t\treg = <0x01c20028 0x4>;\n" @@ -186,7 +198,7 @@ "> -\t\t\tclock-output-names = \"pll6\", \"pll6x2\";\n" "> -\t\t};\n" "> -\n" - "> -\t\tcpu: cpu_clk at 01c20050 {\n" + "> -\t\tcpu: cpu_clk@01c20050 {\n" "> -\t\t\t#clock-cells = <0>;\n" "> -\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n" "> -\t\t\treg = <0x01c20050 0x4>;\n" @@ -201,14 +213,14 @@ "> -\t\t\tclock-output-names = \"cpu\";\n" "> -\t\t};\n" "> -\n" - "> \t\taxi: axi_clk at 01c20050 {\n" + "> \t\taxi: axi_clk@01c20050 {\n" "> \t\t\t#clock-cells = <0>;\n" "> \t\t\tcompatible = \"allwinner,sun8i-a23-axi-clk\";\n" "> @@ -168,22 +85,6 @@\n" "> \t\t\tclock-output-names = \"axi\";\n" "> \t\t};\n" "> \n" - "> -\t\tahb1: ahb1_clk at 01c20054 {\n" + "> -\t\tahb1: ahb1_clk@01c20054 {\n" "> -\t\t\t#clock-cells = <0>;\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" "> -\t\t\treg = <0x01c20054 0x4>;\n" @@ -216,7 +228,7 @@ "> -\t\t\tclock-output-names = \"ahb1\";\n" "> -\t\t};\n" "> -\n" - "> -\t\tapb1: apb1_clk at 01c20054 {\n" + "> -\t\tapb1: apb1_clk@01c20054 {\n" "> -\t\t\t#clock-cells = <0>;\n" "> -\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n" "> -\t\t\treg = <0x01c20054 0x4>;\n" @@ -224,14 +236,14 @@ "> -\t\t\tclock-output-names = \"apb1\";\n" "> -\t\t};\n" "> -\n" - "> \t\tahb1_gates: clk at 01c20060 {\n" + "> \t\tahb1_gates: clk@01c20060 {\n" "> \t\t\t#clock-cells = <1>;\n" "> \t\t\tcompatible = \"allwinner,sun8i-a23-ahb1-gates-clk\";\n" "> @@ -228,36 +129,6 @@\n" "> \t\t\t\t\t\"apb2_uart3\", \"apb2_uart4\";\n" "> \t\t};\n" "> \n" - "> -\t\tmmc0_clk: clk at 01c20088 {\n" + "> -\t\tmmc0_clk: clk@01c20088 {\n" "> -\t\t\t#clock-cells = <1>;\n" "> -\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> -\t\t\treg = <0x01c20088 0x4>;\n" @@ -241,7 +253,7 @@ "> -\t\t\t\t\t \"mmc0_sample\";\n" "> -\t\t};\n" "> -\n" - "> -\t\tmmc1_clk: clk at 01c2008c {\n" + "> -\t\tmmc1_clk: clk@01c2008c {\n" "> -\t\t\t#clock-cells = <1>;\n" "> -\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> -\t\t\treg = <0x01c2008c 0x4>;\n" @@ -251,7 +263,7 @@ "> -\t\t\t\t\t \"mmc1_sample\";\n" "> -\t\t};\n" "> -\n" - "> -\t\tmmc2_clk: clk at 01c20090 {\n" + "> -\t\tmmc2_clk: clk@01c20090 {\n" "> -\t\t\t#clock-cells = <1>;\n" "> -\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> -\t\t\treg = <0x01c20090 0x4>;\n" @@ -261,26 +273,26 @@ "> -\t\t\t\t\t \"mmc2_sample\";\n" "> -\t\t};\n" "> -\n" - "> \t\tmbus_clk: clk at 01c2015c {\n" + "> \t\tmbus_clk: clk@01c2015c {\n" "> \t\t\t#clock-cells = <0>;\n" "> \t\t\tcompatible = \"allwinner,sun8i-a23-mbus-clk\";\n" "> @@ -268,11 +139,6 @@\n" "> \t};\n" "> \n" - "> \tsoc at 01c00000 {\n" + "> \tsoc@01c00000 {\n" "> -\t\tcompatible = \"simple-bus\";\n" "> -\t\t#address-cells = <1>;\n" "> -\t\t#size-cells = <1>;\n" "> -\t\tranges;\n" "> -\n" - "> \t\tdma: dma-controller at 01c02000 {\n" + "> \t\tdma: dma-controller@01c02000 {\n" "> \t\t\tcompatible = \"allwinner,sun8i-a23-dma\";\n" "> \t\t\treg = <0x01c02000 0x1000>;\n" "> @@ -282,75 +148,12 @@\n" "> \t\t\t#dma-cells = <1>;\n" "> \t\t};\n" "> \n" - "> -\t\tmmc0: mmc at 01c0f000 {\n" + "> -\t\tmmc0: mmc@01c0f000 {\n" "> -\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> -\t\t\treg = <0x01c0f000 0x1000>;\n" "> -\t\t\tclocks = <&ahb1_gates 8>,\n" @@ -299,7 +311,7 @@ "> -\t\t\t#size-cells = <0>;\n" "> -\t\t};\n" "> -\n" - "> -\t\tmmc1: mmc at 01c10000 {\n" + "> -\t\tmmc1: mmc@01c10000 {\n" "> -\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> -\t\t\treg = <0x01c10000 0x1000>;\n" "> -\t\t\tclocks = <&ahb1_gates 9>,\n" @@ -318,7 +330,7 @@ "> -\t\t\t#size-cells = <0>;\n" "> -\t\t};\n" "> -\n" - "> -\t\tmmc2: mmc at 01c11000 {\n" + "> -\t\tmmc2: mmc@01c11000 {\n" "> -\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> -\t\t\treg = <0x01c11000 0x1000>;\n" "> -\t\t\tclocks = <&ahb1_gates 10>,\n" @@ -337,7 +349,7 @@ "> -\t\t\t#size-cells = <0>;\n" "> -\t\t};\n" "> -\n" - "> \t\tpio: pinctrl at 01c20800 {\n" + "> \t\tpio: pinctrl@01c20800 {\n" "> \t\t\tcompatible = \"allwinner,sun8i-a23-pinctrl\";\n" "> -\t\t\treg = <0x01c20800 0x400>;\n" "> \t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -351,52 +363,52 @@ "> -\t\t\t#gpio-cells = <3>;\n" "> +\n" "> \n" - "> \t\t\tuart0_pins_a: uart0 at 0 {\n" + "> \t\t\tuart0_pins_a: uart0@0 {\n" "> \t\t\t\tallwinner,pins = \"PF2\", \"PF4\";\n" "> @@ -359,20 +162,6 @@\n" "> \t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> \t\t\t};\n" "> \n" - "> -\t\t\tmmc0_pins_a: mmc0 at 0 {\n" + "> -\t\t\tmmc0_pins_a: mmc0@0 {\n" "> -\t\t\t\tallwinner,pins = \"PF0\",\"PF1\",\"PF2\",\"PF3\",\"PF4\",\"PF5\";\n" "> -\t\t\t\tallwinner,function = \"mmc0\";\n" "> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n" "> -\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> -\t\t\t};\n" "> -\n" - "> -\t\t\tmmc1_pins_a: mmc1 at 0 {\n" + "> -\t\t\tmmc1_pins_a: mmc1@0 {\n" "> -\t\t\t\tallwinner,pins = \"PG0\",\"PG1\",\"PG2\",\"PG3\",\"PG4\",\"PG5\";\n" "> -\t\t\t\tallwinner,function = \"mmc1\";\n" "> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n" "> -\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> -\t\t\t};\n" "> -\n" - "> \t\t\ti2c0_pins_a: i2c0 at 0 {\n" + "> \t\t\ti2c0_pins_a: i2c0@0 {\n" "> \t\t\t\tallwinner,pins = \"PH2\", \"PH3\";\n" "> \t\t\t\tallwinner,function = \"i2c0\";\n" "> @@ -395,38 +184,6 @@\n" "> \t\t\t};\n" "> \t\t};\n" "> \n" - "> -\t\tahb1_rst: reset at 01c202c0 {\n" + "> -\t\tahb1_rst: reset@01c202c0 {\n" "> -\t\t\t#reset-cells = <1>;\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> -\t\t\treg = <0x01c202c0 0xc>;\n" "> -\t\t};\n" "> -\n" - "> -\t\tapb1_rst: reset at 01c202d0 {\n" + "> -\t\tapb1_rst: reset@01c202d0 {\n" "> -\t\t\t#reset-cells = <1>;\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> -\t\t\treg = <0x01c202d0 0x4>;\n" "> -\t\t};\n" "> -\n" - "> -\t\tapb2_rst: reset at 01c202d8 {\n" + "> -\t\tapb2_rst: reset@01c202d8 {\n" "> -\t\t\t#reset-cells = <1>;\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> -\t\t\treg = <0x01c202d8 0x4>;\n" "> -\t\t};\n" "> -\n" - "> -\t\ttimer at 01c20c00 {\n" + "> -\t\ttimer@01c20c00 {\n" "> -\t\t\tcompatible = \"allwinner,sun4i-a10-timer\";\n" "> -\t\t\treg = <0x01c20c00 0xa0>;\n" "> -\t\t\tinterrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -404,20 +416,20 @@ "> -\t\t\tclocks = <&osc24M>;\n" "> -\t\t};\n" "> -\n" - "> -\t\twdt0: watchdog at 01c20ca0 {\n" + "> -\t\twdt0: watchdog@01c20ca0 {\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-wdt\";\n" "> -\t\t\treg = <0x01c20ca0 0x20>;\n" "> -\t\t\tinterrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;\n" "> -\t\t};\n" "> -\n" - "> \t\tlradc: lradc at 01c22800 {\n" + "> \t\tlradc: lradc@01c22800 {\n" "> \t\t\tcompatible = \"allwinner,sun4i-a10-lradc-keys\";\n" "> \t\t\treg = <0x01c22800 0x100>;\n" "> @@ -434,58 +191,6 @@\n" "> \t\t\tstatus = \"disabled\";\n" "> \t\t};\n" "> \n" - "> -\t\tuart0: serial at 01c28000 {\n" + "> -\t\tuart0: serial@01c28000 {\n" "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> -\t\t\treg = <0x01c28000 0x400>;\n" "> -\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -430,7 +442,7 @@ "> -\t\t\tstatus = \"disabled\";\n" "> -\t\t};\n" "> -\n" - "> -\t\tuart1: serial at 01c28400 {\n" + "> -\t\tuart1: serial@01c28400 {\n" "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> -\t\t\treg = <0x01c28400 0x400>;\n" "> -\t\t\tinterrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -443,7 +455,7 @@ "> -\t\t\tstatus = \"disabled\";\n" "> -\t\t};\n" "> -\n" - "> -\t\tuart2: serial at 01c28800 {\n" + "> -\t\tuart2: serial@01c28800 {\n" "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> -\t\t\treg = <0x01c28800 0x400>;\n" "> -\t\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -456,7 +468,7 @@ "> -\t\t\tstatus = \"disabled\";\n" "> -\t\t};\n" "> -\n" - "> -\t\tuart3: serial at 01c28c00 {\n" + "> -\t\tuart3: serial@01c28c00 {\n" "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> -\t\t\treg = <0x01c28c00 0x400>;\n" "> -\t\t\tinterrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -469,7 +481,7 @@ "> -\t\t\tstatus = \"disabled\";\n" "> -\t\t};\n" "> -\n" - "> \t\tuart4: serial at 01c29000 {\n" + "> \t\tuart4: serial@01c29000 {\n" "> \t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> \t\t\treg = <0x01c29000 0x400>;\n" "> @@ -498,136 +203,5 @@\n" @@ -477,7 +489,7 @@ "> \t\t\tstatus = \"disabled\";\n" "> \t\t};\n" "> -\n" - "> -\t\ti2c0: i2c at 01c2ac00 {\n" + "> -\t\ti2c0: i2c@01c2ac00 {\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n" "> -\t\t\treg = <0x01c2ac00 0x400>;\n" "> -\t\t\tinterrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -488,7 +500,7 @@ "> -\t\t\t#size-cells = <0>;\n" "> -\t\t};\n" "> -\n" - "> -\t\ti2c1: i2c at 01c2b000 {\n" + "> -\t\ti2c1: i2c@01c2b000 {\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n" "> -\t\t\treg = <0x01c2b000 0x400>;\n" "> -\t\t\tinterrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -499,7 +511,7 @@ "> -\t\t\t#size-cells = <0>;\n" "> -\t\t};\n" "> -\n" - "> -\t\ti2c2: i2c at 01c2b400 {\n" + "> -\t\ti2c2: i2c@01c2b400 {\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n" "> -\t\t\treg = <0x01c2b400 0x400>;\n" "> -\t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -510,7 +522,7 @@ "> -\t\t\t#size-cells = <0>;\n" "> -\t\t};\n" "> -\n" - "> -\t\tgic: interrupt-controller at 01c81000 {\n" + "> -\t\tgic: interrupt-controller@01c81000 {\n" "> -\t\t\tcompatible = \"arm,cortex-a7-gic\", \"arm,cortex-a15-gic\";\n" "> -\t\t\treg = <0x01c81000 0x1000>,\n" "> -\t\t\t <0x01c82000 0x1000>,\n" @@ -521,14 +533,14 @@ "> -\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" "> -\t\t};\n" "> -\n" - "> -\t\trtc: rtc at 01f00000 {\n" + "> -\t\trtc: rtc@01f00000 {\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-rtc\";\n" "> -\t\t\treg = <0x01f00000 0x54>;\n" "> -\t\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,\n" "> -\t\t\t\t <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;\n" "> -\t\t};\n" "> -\n" - "> -\t\tprcm at 01f01400 {\n" + "> -\t\tprcm@01f01400 {\n" "> -\t\t\tcompatible = \"allwinner,sun8i-a23-prcm\";\n" "> -\t\t\treg = <0x01f01400 0x200>;\n" "> -\n" @@ -572,12 +584,12 @@ "> -\t\t\t};\n" "> -\t\t};\n" "> -\n" - "> -\t\tcpucfg at 01f01c00 {\n" + "> -\t\tcpucfg@01f01c00 {\n" "> -\t\t\tcompatible = \"allwinner,sun8i-a23-cpuconfig\";\n" "> -\t\t\treg = <0x01f01c00 0x300>;\n" "> -\t\t};\n" "> -\n" - "> -\t\tr_uart: serial at 01f02800 {\n" + "> -\t\tr_uart: serial@01f02800 {\n" "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> -\t\t\treg = <0x01f02800 0x400>;\n" "> -\t\t\tinterrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -588,7 +600,7 @@ "> -\t\t\tstatus = \"disabled\";\n" "> -\t\t};\n" "> -\n" - "> -\t\tr_pio: pinctrl at 01f02c00 {\n" + "> -\t\tr_pio: pinctrl@01f02c00 {\n" "> -\t\t\tcompatible = \"allwinner,sun8i-a23-r-pinctrl\";\n" "> -\t\t\treg = <0x01f02c00 0x400>;\n" "> -\t\t\tinterrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -600,7 +612,7 @@ "> -\t\t\t#size-cells = <0>;\n" "> -\t\t\t#gpio-cells = <3>;\n" "> -\n" - "> -\t\t\tr_uart_pins_a: r_uart at 0 {\n" + "> -\t\t\tr_uart_pins_a: r_uart@0 {\n" "> -\t\t\t\tallwinner,pins = \"PL2\", \"PL3\";\n" "> -\t\t\t\tallwinner,function = \"s_uart\";\n" "> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" @@ -618,7 +630,7 @@ "> +/*\n" "> + * Copyright 2014 Chen-Yu Tsai\n" "> + *\n" - "> + * Chen-Yu Tsai <wens@csie.org>\n" + "> + * Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>\n" "> + *\n" "> + * This file is dual-licensed: you can use it either under the terms\n" "> + * of the GPL or the X11 license, at your option. Note that this dual\n" @@ -674,7 +686,7 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tframebuffer at 0 {\n" + "> +\t\tframebuffer@0 {\n" "> +\t\t\tcompatible = \"allwinner,simple-framebuffer\",\n" "> +\t\t\t\t \"simple-framebuffer\";\n" "> +\t\t\tallwinner,pipeline = \"de_be0-lcd0\";\n" @@ -712,7 +724,7 @@ "> +\t\t\tclock-output-names = \"osc32k\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll1: clk at 01c20000 {\n" + "> +\t\tpll1: clk@01c20000 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n" "> +\t\t\treg = <0x01c20000 0x4>;\n" @@ -720,7 +732,7 @@ "> +\t\t\tclock-output-names = \"pll1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll6: clk at 01c20028 {\n" + "> +\t\tpll6: clk@01c20028 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" "> +\t\t\treg = <0x01c20028 0x4>;\n" @@ -728,7 +740,7 @@ "> +\t\t\tclock-output-names = \"pll6\", \"pll6x2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu: cpu_clk at 01c20050 {\n" + "> +\t\tcpu: cpu_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -744,7 +756,7 @@ "> +\t\t};\n" "> +\n" "> +\n" - "> +\t\tahb1: ahb1_clk at 01c20054 {\n" + "> +\t\tahb1: ahb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -752,7 +764,7 @@ "> +\t\t\tclock-output-names = \"ahb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb1: apb1_clk at 01c20054 {\n" + "> +\t\tapb1: apb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -760,7 +772,7 @@ "> +\t\t\tclock-output-names = \"apb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc0_clk: clk at 01c20088 {\n" + "> +\t\tmmc0_clk: clk@01c20088 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c20088 0x4>;\n" @@ -770,7 +782,7 @@ "> +\t\t\t\t\t \"mmc0_sample\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc1_clk: clk at 01c2008c {\n" + "> +\t\tmmc1_clk: clk@01c2008c {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c2008c 0x4>;\n" @@ -780,7 +792,7 @@ "> +\t\t\t\t\t \"mmc1_sample\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc2_clk: clk at 01c20090 {\n" + "> +\t\tmmc2_clk: clk@01c20090 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c20090 0x4>;\n" @@ -792,14 +804,14 @@ "> +\n" "> +\t};\n" "> +\n" - "> +\tsoc at 01c00000 {\n" + "> +\tsoc@01c00000 {\n" "> +\t\tcompatible = \"simple-bus\";\n" "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" "> +\n" - "> +\t\tmmc0: mmc at 01c0f000 {\n" + "> +\t\tmmc0: mmc@01c0f000 {\n" "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c0f000 0x1000>;\n" "> +\t\t\tclocks = <&ahb1_gates 8>,\n" @@ -818,7 +830,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc1: mmc at 01c10000 {\n" + "> +\t\tmmc1: mmc@01c10000 {\n" "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c10000 0x1000>;\n" "> +\t\t\tclocks = <&ahb1_gates 9>,\n" @@ -837,7 +849,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc2: mmc at 01c11000 {\n" + "> +\t\tmmc2: mmc@01c11000 {\n" "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c11000 0x1000>;\n" "> +\t\t\tclocks = <&ahb1_gates 10>,\n" @@ -856,7 +868,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tpio: pinctrl at 01c20800 {\n" + "> +\t\tpio: pinctrl@01c20800 {\n" "> +\t\t\treg = <0x01c20800 0x400>;\n" "> +\t\t\tclocks = <&apb1_gates 5>;\n" "> +\t\t\tgpio-controller;\n" @@ -865,14 +877,14 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t\t#gpio-cells = <3>;\n" "> +\n" - "> +\t\t\tmmc0_pins_a: mmc0 at 0 {\n" + "> +\t\t\tmmc0_pins_a: mmc0@0 {\n" "> +\t\t\t\tallwinner,pins = \"PF0\",\"PF1\",\"PF2\",\"PF3\",\"PF4\",\"PF5\";\n" "> +\t\t\t\tallwinner,function = \"mmc0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc1_pins_a: mmc1 at 0 {\n" + "> +\t\t\tmmc1_pins_a: mmc1@0 {\n" "> +\t\t\t\tallwinner,pins = \"PG0\",\"PG1\",\"PG2\",\"PG3\",\"PG4\",\"PG5\";\n" "> +\t\t\t\tallwinner,function = \"mmc1\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n" @@ -880,25 +892,25 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb1_rst: reset at 01c202c0 {\n" + "> +\t\tahb1_rst: reset@01c202c0 {\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> +\t\t\treg = <0x01c202c0 0xc>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb1_rst: reset at 01c202d0 {\n" + "> +\t\tapb1_rst: reset@01c202d0 {\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> +\t\t\treg = <0x01c202d0 0x4>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb2_rst: reset at 01c202d8 {\n" + "> +\t\tapb2_rst: reset@01c202d8 {\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> +\t\t\treg = <0x01c202d8 0x4>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ttimer at 01c20c00 {\n" + "> +\t\ttimer@01c20c00 {\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-timer\";\n" "> +\t\t\treg = <0x01c20c00 0xa0>;\n" "> +\t\t\tinterrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -906,13 +918,13 @@ "> +\t\t\tclocks = <&osc24M>;\n" "> +\t\t};\n" "> +\n" - "> +\t\twdt0: watchdog at 01c20ca0 {\n" + "> +\t\twdt0: watchdog@01c20ca0 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-wdt\";\n" "> +\t\t\treg = <0x01c20ca0 0x20>;\n" "> +\t\t\tinterrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart0: serial at 01c28000 {\n" + "> +\t\tuart0: serial@01c28000 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -925,7 +937,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart1: serial at 01c28400 {\n" + "> +\t\tuart1: serial@01c28400 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28400 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -938,7 +950,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart2: serial at 01c28800 {\n" + "> +\t\tuart2: serial@01c28800 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28800 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -951,7 +963,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart3: serial at 01c28c00 {\n" + "> +\t\tuart3: serial@01c28c00 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28c00 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -964,7 +976,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c0: i2c at 01c2ac00 {\n" + "> +\t\ti2c0: i2c@01c2ac00 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n" "> +\t\t\treg = <0x01c2ac00 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -975,7 +987,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c1: i2c at 01c2b000 {\n" + "> +\t\ti2c1: i2c@01c2b000 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n" "> +\t\t\treg = <0x01c2b000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -986,7 +998,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c2: i2c at 01c2b400 {\n" + "> +\t\ti2c2: i2c@01c2b400 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n" "> +\t\t\treg = <0x01c2b400 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -997,7 +1009,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgic: interrupt-controller at 01c81000 {\n" + "> +\t\tgic: interrupt-controller@01c81000 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7-gic\", \"arm,cortex-a15-gic\";\n" "> +\t\t\treg = <0x01c81000 0x1000>,\n" "> +\t\t\t <0x01c82000 0x1000>,\n" @@ -1008,14 +1020,14 @@ "> +\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" "> +\t\t};\n" "> +\n" - "> +\t\trtc: rtc at 01f00000 {\n" + "> +\t\trtc: rtc@01f00000 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-rtc\";\n" "> +\t\t\treg = <0x01f00000 0x54>;\n" "> +\t\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,\n" "> +\t\t\t\t <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tprcm at 01f01400 {\n" + "> +\t\tprcm@01f01400 {\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-prcm\";\n" "> +\t\t\treg = <0x01f01400 0x200>;\n" "> +\n" @@ -1059,12 +1071,12 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpucfg at 01f01c00 {\n" + "> +\t\tcpucfg@01f01c00 {\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-cpuconfig\";\n" "> +\t\t\treg = <0x01f01c00 0x300>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tr_uart: serial at 01f02800 {\n" + "> +\t\tr_uart: serial@01f02800 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01f02800 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -1075,7 +1087,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tr_pio: pinctrl at 01f02c00 {\n" + "> +\t\tr_pio: pinctrl@01f02c00 {\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-r-pinctrl\";\n" "> +\t\t\treg = <0x01f02c00 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -1087,7 +1099,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t\t#gpio-cells = <3>;\n" "> +\n" - "> +\t\t\tr_uart_pins_a: r_uart at 0 {\n" + "> +\t\t\tr_uart_pins_a: r_uart@0 {\n" "> +\t\t\t\tallwinner,pins = \"PL2\", \"PL3\";\n" "> +\t\t\t\tallwinner,function = \"s_uart\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" @@ -1117,13 +1129,6 @@ "-- \n" "Maxime Ripard, Free Electrons\n" "Embedded Linux, Kernel and Android engineering\n" - "http://free-electrons.com\n" - "-------------- next part --------------\n" - "A non-text attachment was scrubbed...\n" - "Name: signature.asc\n" - "Type: application/pgp-signature\n" - "Size: 819 bytes\n" - "Desc: Digital signature\n" - URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20150510/1821ffb1/attachment-0001.sig> + http://free-electrons.com -dc4a2086779727b08c61f9b0bfa11fb002b61355f7c8f0000e18edbba96e1955 +6064414e1a2c3bc9d45fa341c0c480182e74a4159d0188c7e9a4a599ab7f4dd7
diff --git a/a/1.txt b/N2/1.txt index 9c0bf4f..fe7c00a 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -105,7 +105,7 @@ It adds a new compatible to boards. > - #size-cells = <1>; > - ranges; > - -> - framebuffer at 0 { +> - framebuffer@0 { > - compatible = "allwinner,simple-framebuffer", > - "simple-framebuffer"; > - allwinner,pipeline = "de_be0-lcd0"; @@ -155,7 +155,7 @@ It updates a CPU enable method. > - clock-output-names = "osc32k"; > - }; > - -> - pll1: clk at 01c20000 { +> - pll1: clk@01c20000 { > - #clock-cells = <0>; > - compatible = "allwinner,sun8i-a23-pll1-clk"; > - reg = <0x01c20000 0x4>; @@ -170,7 +170,7 @@ It updates a CPU enable method. > clock-output-names = "pll5"; > }; > -> - pll6: clk at 01c20028 { +> - pll6: clk@01c20028 { > - #clock-cells = <1>; > - compatible = "allwinner,sun6i-a31-pll6-clk"; > - reg = <0x01c20028 0x4>; @@ -178,7 +178,7 @@ It updates a CPU enable method. > - clock-output-names = "pll6", "pll6x2"; > - }; > - -> - cpu: cpu_clk at 01c20050 { +> - cpu: cpu_clk@01c20050 { > - #clock-cells = <0>; > - compatible = "allwinner,sun4i-a10-cpu-clk"; > - reg = <0x01c20050 0x4>; @@ -193,14 +193,14 @@ It updates a CPU enable method. > - clock-output-names = "cpu"; > - }; > - -> axi: axi_clk at 01c20050 { +> axi: axi_clk@01c20050 { > #clock-cells = <0>; > compatible = "allwinner,sun8i-a23-axi-clk"; > @@ -168,22 +85,6 @@ > clock-output-names = "axi"; > }; > -> - ahb1: ahb1_clk at 01c20054 { +> - ahb1: ahb1_clk@01c20054 { > - #clock-cells = <0>; > - compatible = "allwinner,sun6i-a31-ahb1-clk"; > - reg = <0x01c20054 0x4>; @@ -208,7 +208,7 @@ It updates a CPU enable method. > - clock-output-names = "ahb1"; > - }; > - -> - apb1: apb1_clk at 01c20054 { +> - apb1: apb1_clk@01c20054 { > - #clock-cells = <0>; > - compatible = "allwinner,sun4i-a10-apb0-clk"; > - reg = <0x01c20054 0x4>; @@ -216,14 +216,14 @@ It updates a CPU enable method. > - clock-output-names = "apb1"; > - }; > - -> ahb1_gates: clk at 01c20060 { +> ahb1_gates: clk@01c20060 { > #clock-cells = <1>; > compatible = "allwinner,sun8i-a23-ahb1-gates-clk"; > @@ -228,36 +129,6 @@ > "apb2_uart3", "apb2_uart4"; > }; > -> - mmc0_clk: clk at 01c20088 { +> - mmc0_clk: clk@01c20088 { > - #clock-cells = <1>; > - compatible = "allwinner,sun4i-a10-mmc-clk"; > - reg = <0x01c20088 0x4>; @@ -233,7 +233,7 @@ It updates a CPU enable method. > - "mmc0_sample"; > - }; > - -> - mmc1_clk: clk at 01c2008c { +> - mmc1_clk: clk@01c2008c { > - #clock-cells = <1>; > - compatible = "allwinner,sun4i-a10-mmc-clk"; > - reg = <0x01c2008c 0x4>; @@ -243,7 +243,7 @@ It updates a CPU enable method. > - "mmc1_sample"; > - }; > - -> - mmc2_clk: clk at 01c20090 { +> - mmc2_clk: clk@01c20090 { > - #clock-cells = <1>; > - compatible = "allwinner,sun4i-a10-mmc-clk"; > - reg = <0x01c20090 0x4>; @@ -253,26 +253,26 @@ It updates a CPU enable method. > - "mmc2_sample"; > - }; > - -> mbus_clk: clk at 01c2015c { +> mbus_clk: clk@01c2015c { > #clock-cells = <0>; > compatible = "allwinner,sun8i-a23-mbus-clk"; > @@ -268,11 +139,6 @@ > }; > -> soc at 01c00000 { +> soc@01c00000 { > - compatible = "simple-bus"; > - #address-cells = <1>; > - #size-cells = <1>; > - ranges; > - -> dma: dma-controller at 01c02000 { +> dma: dma-controller@01c02000 { > compatible = "allwinner,sun8i-a23-dma"; > reg = <0x01c02000 0x1000>; > @@ -282,75 +148,12 @@ > #dma-cells = <1>; > }; > -> - mmc0: mmc at 01c0f000 { +> - mmc0: mmc@01c0f000 { > - compatible = "allwinner,sun5i-a13-mmc"; > - reg = <0x01c0f000 0x1000>; > - clocks = <&ahb1_gates 8>, @@ -291,7 +291,7 @@ It updates a CPU enable method. > - #size-cells = <0>; > - }; > - -> - mmc1: mmc at 01c10000 { +> - mmc1: mmc@01c10000 { > - compatible = "allwinner,sun5i-a13-mmc"; > - reg = <0x01c10000 0x1000>; > - clocks = <&ahb1_gates 9>, @@ -310,7 +310,7 @@ It updates a CPU enable method. > - #size-cells = <0>; > - }; > - -> - mmc2: mmc at 01c11000 { +> - mmc2: mmc@01c11000 { > - compatible = "allwinner,sun5i-a13-mmc"; > - reg = <0x01c11000 0x1000>; > - clocks = <&ahb1_gates 10>, @@ -329,7 +329,7 @@ It updates a CPU enable method. > - #size-cells = <0>; > - }; > - -> pio: pinctrl at 01c20800 { +> pio: pinctrl@01c20800 { > compatible = "allwinner,sun8i-a23-pinctrl"; > - reg = <0x01c20800 0x400>; > interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -343,52 +343,52 @@ It updates a CPU enable method. > - #gpio-cells = <3>; > + > -> uart0_pins_a: uart0 at 0 { +> uart0_pins_a: uart0@0 { > allwinner,pins = "PF2", "PF4"; > @@ -359,20 +162,6 @@ > allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > }; > -> - mmc0_pins_a: mmc0 at 0 { +> - mmc0_pins_a: mmc0@0 { > - allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; > - allwinner,function = "mmc0"; > - allwinner,drive = <SUN4I_PINCTRL_30_MA>; > - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > - }; > - -> - mmc1_pins_a: mmc1 at 0 { +> - mmc1_pins_a: mmc1@0 { > - allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5"; > - allwinner,function = "mmc1"; > - allwinner,drive = <SUN4I_PINCTRL_30_MA>; > - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > - }; > - -> i2c0_pins_a: i2c0 at 0 { +> i2c0_pins_a: i2c0@0 { > allwinner,pins = "PH2", "PH3"; > allwinner,function = "i2c0"; > @@ -395,38 +184,6 @@ > }; > }; > -> - ahb1_rst: reset at 01c202c0 { +> - ahb1_rst: reset@01c202c0 { > - #reset-cells = <1>; > - compatible = "allwinner,sun6i-a31-clock-reset"; > - reg = <0x01c202c0 0xc>; > - }; > - -> - apb1_rst: reset at 01c202d0 { +> - apb1_rst: reset@01c202d0 { > - #reset-cells = <1>; > - compatible = "allwinner,sun6i-a31-clock-reset"; > - reg = <0x01c202d0 0x4>; > - }; > - -> - apb2_rst: reset at 01c202d8 { +> - apb2_rst: reset@01c202d8 { > - #reset-cells = <1>; > - compatible = "allwinner,sun6i-a31-clock-reset"; > - reg = <0x01c202d8 0x4>; > - }; > - -> - timer at 01c20c00 { +> - timer@01c20c00 { > - compatible = "allwinner,sun4i-a10-timer"; > - reg = <0x01c20c00 0xa0>; > - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -396,20 +396,20 @@ It updates a CPU enable method. > - clocks = <&osc24M>; > - }; > - -> - wdt0: watchdog at 01c20ca0 { +> - wdt0: watchdog@01c20ca0 { > - compatible = "allwinner,sun6i-a31-wdt"; > - reg = <0x01c20ca0 0x20>; > - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; > - }; > - -> lradc: lradc at 01c22800 { +> lradc: lradc@01c22800 { > compatible = "allwinner,sun4i-a10-lradc-keys"; > reg = <0x01c22800 0x100>; > @@ -434,58 +191,6 @@ > status = "disabled"; > }; > -> - uart0: serial at 01c28000 { +> - uart0: serial@01c28000 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x01c28000 0x400>; > - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -422,7 +422,7 @@ It updates a CPU enable method. > - status = "disabled"; > - }; > - -> - uart1: serial at 01c28400 { +> - uart1: serial@01c28400 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x01c28400 0x400>; > - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -435,7 +435,7 @@ It updates a CPU enable method. > - status = "disabled"; > - }; > - -> - uart2: serial at 01c28800 { +> - uart2: serial@01c28800 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x01c28800 0x400>; > - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -448,7 +448,7 @@ It updates a CPU enable method. > - status = "disabled"; > - }; > - -> - uart3: serial at 01c28c00 { +> - uart3: serial@01c28c00 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x01c28c00 0x400>; > - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -461,7 +461,7 @@ It updates a CPU enable method. > - status = "disabled"; > - }; > - -> uart4: serial at 01c29000 { +> uart4: serial@01c29000 { > compatible = "snps,dw-apb-uart"; > reg = <0x01c29000 0x400>; > @@ -498,136 +203,5 @@ @@ -469,7 +469,7 @@ It updates a CPU enable method. > status = "disabled"; > }; > - -> - i2c0: i2c at 01c2ac00 { +> - i2c0: i2c@01c2ac00 { > - compatible = "allwinner,sun6i-a31-i2c"; > - reg = <0x01c2ac00 0x400>; > - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -480,7 +480,7 @@ It updates a CPU enable method. > - #size-cells = <0>; > - }; > - -> - i2c1: i2c at 01c2b000 { +> - i2c1: i2c@01c2b000 { > - compatible = "allwinner,sun6i-a31-i2c"; > - reg = <0x01c2b000 0x400>; > - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -491,7 +491,7 @@ It updates a CPU enable method. > - #size-cells = <0>; > - }; > - -> - i2c2: i2c at 01c2b400 { +> - i2c2: i2c@01c2b400 { > - compatible = "allwinner,sun6i-a31-i2c"; > - reg = <0x01c2b400 0x400>; > - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; @@ -502,7 +502,7 @@ It updates a CPU enable method. > - #size-cells = <0>; > - }; > - -> - gic: interrupt-controller at 01c81000 { +> - gic: interrupt-controller@01c81000 { > - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; > - reg = <0x01c81000 0x1000>, > - <0x01c82000 0x1000>, @@ -513,14 +513,14 @@ It updates a CPU enable method. > - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > - }; > - -> - rtc: rtc at 01f00000 { +> - rtc: rtc@01f00000 { > - compatible = "allwinner,sun6i-a31-rtc"; > - reg = <0x01f00000 0x54>; > - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > - }; > - -> - prcm at 01f01400 { +> - prcm@01f01400 { > - compatible = "allwinner,sun8i-a23-prcm"; > - reg = <0x01f01400 0x200>; > - @@ -564,12 +564,12 @@ It updates a CPU enable method. > - }; > - }; > - -> - cpucfg at 01f01c00 { +> - cpucfg@01f01c00 { > - compatible = "allwinner,sun8i-a23-cpuconfig"; > - reg = <0x01f01c00 0x300>; > - }; > - -> - r_uart: serial at 01f02800 { +> - r_uart: serial@01f02800 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x01f02800 0x400>; > - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; @@ -580,7 +580,7 @@ It updates a CPU enable method. > - status = "disabled"; > - }; > - -> - r_pio: pinctrl at 01f02c00 { +> - r_pio: pinctrl@01f02c00 { > - compatible = "allwinner,sun8i-a23-r-pinctrl"; > - reg = <0x01f02c00 0x400>; > - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -592,7 +592,7 @@ It updates a CPU enable method. > - #size-cells = <0>; > - #gpio-cells = <3>; > - -> - r_uart_pins_a: r_uart at 0 { +> - r_uart_pins_a: r_uart@0 { > - allwinner,pins = "PL2", "PL3"; > - allwinner,function = "s_uart"; > - allwinner,drive = <SUN4I_PINCTRL_10_MA>; @@ -666,7 +666,7 @@ It updates a CPU enable method. > + #size-cells = <1>; > + ranges; > + -> + framebuffer at 0 { +> + framebuffer@0 { > + compatible = "allwinner,simple-framebuffer", > + "simple-framebuffer"; > + allwinner,pipeline = "de_be0-lcd0"; @@ -704,7 +704,7 @@ It updates a CPU enable method. > + clock-output-names = "osc32k"; > + }; > + -> + pll1: clk at 01c20000 { +> + pll1: clk@01c20000 { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-a23-pll1-clk"; > + reg = <0x01c20000 0x4>; @@ -712,7 +712,7 @@ It updates a CPU enable method. > + clock-output-names = "pll1"; > + }; > + -> + pll6: clk at 01c20028 { +> + pll6: clk@01c20028 { > + #clock-cells = <1>; > + compatible = "allwinner,sun6i-a31-pll6-clk"; > + reg = <0x01c20028 0x4>; @@ -720,7 +720,7 @@ It updates a CPU enable method. > + clock-output-names = "pll6", "pll6x2"; > + }; > + -> + cpu: cpu_clk at 01c20050 { +> + cpu: cpu_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-cpu-clk"; > + reg = <0x01c20050 0x4>; @@ -736,7 +736,7 @@ It updates a CPU enable method. > + }; > + > + -> + ahb1: ahb1_clk at 01c20054 { +> + ahb1: ahb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-ahb1-clk"; > + reg = <0x01c20054 0x4>; @@ -744,7 +744,7 @@ It updates a CPU enable method. > + clock-output-names = "ahb1"; > + }; > + -> + apb1: apb1_clk at 01c20054 { +> + apb1: apb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb0-clk"; > + reg = <0x01c20054 0x4>; @@ -752,7 +752,7 @@ It updates a CPU enable method. > + clock-output-names = "apb1"; > + }; > + -> + mmc0_clk: clk at 01c20088 { +> + mmc0_clk: clk@01c20088 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20088 0x4>; @@ -762,7 +762,7 @@ It updates a CPU enable method. > + "mmc0_sample"; > + }; > + -> + mmc1_clk: clk at 01c2008c { +> + mmc1_clk: clk@01c2008c { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c2008c 0x4>; @@ -772,7 +772,7 @@ It updates a CPU enable method. > + "mmc1_sample"; > + }; > + -> + mmc2_clk: clk at 01c20090 { +> + mmc2_clk: clk@01c20090 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20090 0x4>; @@ -784,14 +784,14 @@ It updates a CPU enable method. > + > + }; > + -> + soc at 01c00000 { +> + soc@01c00000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + -> + mmc0: mmc at 01c0f000 { +> + mmc0: mmc@01c0f000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c0f000 0x1000>; > + clocks = <&ahb1_gates 8>, @@ -810,7 +810,7 @@ It updates a CPU enable method. > + #size-cells = <0>; > + }; > + -> + mmc1: mmc at 01c10000 { +> + mmc1: mmc@01c10000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c10000 0x1000>; > + clocks = <&ahb1_gates 9>, @@ -829,7 +829,7 @@ It updates a CPU enable method. > + #size-cells = <0>; > + }; > + -> + mmc2: mmc at 01c11000 { +> + mmc2: mmc@01c11000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c11000 0x1000>; > + clocks = <&ahb1_gates 10>, @@ -848,7 +848,7 @@ It updates a CPU enable method. > + #size-cells = <0>; > + }; > + -> + pio: pinctrl at 01c20800 { +> + pio: pinctrl@01c20800 { > + reg = <0x01c20800 0x400>; > + clocks = <&apb1_gates 5>; > + gpio-controller; @@ -857,14 +857,14 @@ It updates a CPU enable method. > + #size-cells = <0>; > + #gpio-cells = <3>; > + -> + mmc0_pins_a: mmc0 at 0 { +> + mmc0_pins_a: mmc0@0 { > + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; > + allwinner,function = "mmc0"; > + allwinner,drive = <SUN4I_PINCTRL_30_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + mmc1_pins_a: mmc1 at 0 { +> + mmc1_pins_a: mmc1@0 { > + allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5"; > + allwinner,function = "mmc1"; > + allwinner,drive = <SUN4I_PINCTRL_30_MA>; @@ -872,25 +872,25 @@ It updates a CPU enable method. > + }; > + }; > + -> + ahb1_rst: reset at 01c202c0 { +> + ahb1_rst: reset@01c202c0 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-clock-reset"; > + reg = <0x01c202c0 0xc>; > + }; > + -> + apb1_rst: reset at 01c202d0 { +> + apb1_rst: reset@01c202d0 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-clock-reset"; > + reg = <0x01c202d0 0x4>; > + }; > + -> + apb2_rst: reset at 01c202d8 { +> + apb2_rst: reset@01c202d8 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-clock-reset"; > + reg = <0x01c202d8 0x4>; > + }; > + -> + timer at 01c20c00 { +> + timer@01c20c00 { > + compatible = "allwinner,sun4i-a10-timer"; > + reg = <0x01c20c00 0xa0>; > + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -898,13 +898,13 @@ It updates a CPU enable method. > + clocks = <&osc24M>; > + }; > + -> + wdt0: watchdog at 01c20ca0 { +> + wdt0: watchdog@01c20ca0 { > + compatible = "allwinner,sun6i-a31-wdt"; > + reg = <0x01c20ca0 0x20>; > + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; > + }; > + -> + uart0: serial at 01c28000 { +> + uart0: serial@01c28000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28000 0x400>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -917,7 +917,7 @@ It updates a CPU enable method. > + status = "disabled"; > + }; > + -> + uart1: serial at 01c28400 { +> + uart1: serial@01c28400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28400 0x400>; > + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -930,7 +930,7 @@ It updates a CPU enable method. > + status = "disabled"; > + }; > + -> + uart2: serial at 01c28800 { +> + uart2: serial@01c28800 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28800 0x400>; > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -943,7 +943,7 @@ It updates a CPU enable method. > + status = "disabled"; > + }; > + -> + uart3: serial at 01c28c00 { +> + uart3: serial@01c28c00 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28c00 0x400>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -956,7 +956,7 @@ It updates a CPU enable method. > + status = "disabled"; > + }; > + -> + i2c0: i2c at 01c2ac00 { +> + i2c0: i2c@01c2ac00 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2ac00 0x400>; > + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -967,7 +967,7 @@ It updates a CPU enable method. > + #size-cells = <0>; > + }; > + -> + i2c1: i2c at 01c2b000 { +> + i2c1: i2c@01c2b000 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2b000 0x400>; > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -978,7 +978,7 @@ It updates a CPU enable method. > + #size-cells = <0>; > + }; > + -> + i2c2: i2c at 01c2b400 { +> + i2c2: i2c@01c2b400 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2b400 0x400>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; @@ -989,7 +989,7 @@ It updates a CPU enable method. > + #size-cells = <0>; > + }; > + -> + gic: interrupt-controller at 01c81000 { +> + gic: interrupt-controller@01c81000 { > + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; > + reg = <0x01c81000 0x1000>, > + <0x01c82000 0x1000>, @@ -1000,14 +1000,14 @@ It updates a CPU enable method. > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + -> + rtc: rtc at 01f00000 { +> + rtc: rtc@01f00000 { > + compatible = "allwinner,sun6i-a31-rtc"; > + reg = <0x01f00000 0x54>; > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > + }; > + -> + prcm at 01f01400 { +> + prcm@01f01400 { > + compatible = "allwinner,sun8i-a23-prcm"; > + reg = <0x01f01400 0x200>; > + @@ -1051,12 +1051,12 @@ It updates a CPU enable method. > + }; > + }; > + -> + cpucfg at 01f01c00 { +> + cpucfg@01f01c00 { > + compatible = "allwinner,sun8i-a23-cpuconfig"; > + reg = <0x01f01c00 0x300>; > + }; > + -> + r_uart: serial at 01f02800 { +> + r_uart: serial@01f02800 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01f02800 0x400>; > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; @@ -1067,7 +1067,7 @@ It updates a CPU enable method. > + status = "disabled"; > + }; > + -> + r_pio: pinctrl at 01f02c00 { +> + r_pio: pinctrl@01f02c00 { > + compatible = "allwinner,sun8i-a23-r-pinctrl"; > + reg = <0x01f02c00 0x400>; > + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -1079,7 +1079,7 @@ It updates a CPU enable method. > + #size-cells = <0>; > + #gpio-cells = <3>; > + -> + r_uart_pins_a: r_uart at 0 { +> + r_uart_pins_a: r_uart@0 { > + allwinner,pins = "PL2", "PL3"; > + allwinner,function = "s_uart"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; @@ -1110,10 +1110,3 @@ Maxime Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --------------- next part -------------- -A non-text attachment was scrubbed... -Name: signature.asc -Type: application/pgp-signature -Size: 819 bytes -Desc: Digital signature -URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20150510/1821ffb1/attachment-0001.sig> diff --git a/N2/2.bin b/N2/2.bin new file mode 100644 index 0000000..3e879c7 --- /dev/null +++ b/N2/2.bin @@ -0,0 +1,17 @@ +-----BEGIN PGP SIGNATURE----- +Version: GnuPG v1 + +iQIcBAEBAgAGBQJVTzXRAAoJEBx+YmzsjxAgj8gQAJuO0eGtdyu+LSp12avsPtwt +8qx8GiJ9JM5zJHL2vrLTfW2ntsYUCDU9b+Z02oevo59giYrBWNSzvkUgsu1RQE0U +jrxhL7XuWSXfUXeF4IsnqpZhLStacT+RlZg0H+SDc6hBATO1P42JAwQ8zHRW5UwK +xOimGaMtpJ2fYF8kwUgOEB3/N4BMmelQ6K4YPtqlmpB6RjZzZ1uYaRDGtFPztJOP +zhqwrQUXv28yVO8HybPSSTZwReparWZyOjn5QS2OpxL91mni0xkoTumPdjOonlKi +Gf7Lc6J+esog4NyqGxjrNZUww26Z6KlL5ehkqfVpYDoPTZ/Yhe6jrewx6cL1cjVT +A5/GOubBkPaVV+DfwAiTBTDVrhilOrn2sKKTqVQ4mPbLz49ufImQcwQw5s7kocar +Vko6+dZfyTPz9eh0EsMMvJ53PJRrrMSWxhSw+h5EH6Knq2f/E/AU9BbYzhcXW3yB +cgv8FzMW/5S7zgo7M2V9ay7YCPjGNuo7SHGdqR/3JWWcHYhWa+dP8cR7HW15u0mC +/0n1MfTG/Dfk25Ae2WVaf6cJep0M7k3PZyuYkLzvk8J0EatVb/8DM5DxwRvsPR26 +pQL+DQg9n7PQ5EE4SDV+A4/qxaIdeih9hOru4Fwiyb/kXpuAlaRrst9qxswLTK4b +7hGPAc6Yh+zprvr6WFM+ +=2bSM +-----END PGP SIGNATURE----- diff --git a/N2/2.hdr b/N2/2.hdr new file mode 100644 index 0000000..3237378 --- /dev/null +++ b/N2/2.hdr @@ -0,0 +1,2 @@ +Content-Type: application/pgp-signature; name="signature.asc" +Content-Description: Digital signature diff --git a/a/content_digest b/N2/content_digest index fe1e546..43e0f9f 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,10 +1,21 @@ "ref\01431240383-12763-1-git-send-email-vishnupatekar0510@gmail.com\0" "ref\01431240383-12763-5-git-send-email-vishnupatekar0510@gmail.com\0" - "From\0maxime.ripard@free-electrons.com (Maxime Ripard)\0" - "Subject\0[PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi\0" + "From\0Maxime Ripard <maxime.ripard@free-electrons.com>\0" + "Subject\0Re: [PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi\0" "Date\0Sun, 10 May 2015 12:41:21 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" - "\00:1\0" + "To\0Vishnu Patekar <vishnupatekar0510@gmail.com>\0" + "Cc\0emilio@elopez.com.ar" + linus.walleij@linaro.org + robh+dt@kernel.org + hdegoede@redhat.com + wens@csie.org + jenskuske@gmail.com + arnd@arndb.de + linux-arm-kernel@lists.infradead.org + linux-kernel@vger.kernel.org + linux-sunxi@googlegroups.com + " devicetree@vger.kernel.org\0" + "\01:1\0" "b\0" "Hi,\n" "\n" @@ -113,7 +124,7 @@ "> -\t\t#size-cells = <1>;\n" "> -\t\tranges;\n" "> -\n" - "> -\t\tframebuffer at 0 {\n" + "> -\t\tframebuffer@0 {\n" "> -\t\t\tcompatible = \"allwinner,simple-framebuffer\",\n" "> -\t\t\t\t \"simple-framebuffer\";\n" "> -\t\t\tallwinner,pipeline = \"de_be0-lcd0\";\n" @@ -163,7 +174,7 @@ "> -\t\t\tclock-output-names = \"osc32k\";\n" "> -\t\t};\n" "> -\n" - "> -\t\tpll1: clk at 01c20000 {\n" + "> -\t\tpll1: clk@01c20000 {\n" "> -\t\t\t#clock-cells = <0>;\n" "> -\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n" "> -\t\t\treg = <0x01c20000 0x4>;\n" @@ -178,7 +189,7 @@ "> \t\t\tclock-output-names = \"pll5\";\n" "> \t\t};\n" "> \n" - "> -\t\tpll6: clk at 01c20028 {\n" + "> -\t\tpll6: clk@01c20028 {\n" "> -\t\t\t#clock-cells = <1>;\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" "> -\t\t\treg = <0x01c20028 0x4>;\n" @@ -186,7 +197,7 @@ "> -\t\t\tclock-output-names = \"pll6\", \"pll6x2\";\n" "> -\t\t};\n" "> -\n" - "> -\t\tcpu: cpu_clk at 01c20050 {\n" + "> -\t\tcpu: cpu_clk@01c20050 {\n" "> -\t\t\t#clock-cells = <0>;\n" "> -\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n" "> -\t\t\treg = <0x01c20050 0x4>;\n" @@ -201,14 +212,14 @@ "> -\t\t\tclock-output-names = \"cpu\";\n" "> -\t\t};\n" "> -\n" - "> \t\taxi: axi_clk at 01c20050 {\n" + "> \t\taxi: axi_clk@01c20050 {\n" "> \t\t\t#clock-cells = <0>;\n" "> \t\t\tcompatible = \"allwinner,sun8i-a23-axi-clk\";\n" "> @@ -168,22 +85,6 @@\n" "> \t\t\tclock-output-names = \"axi\";\n" "> \t\t};\n" "> \n" - "> -\t\tahb1: ahb1_clk at 01c20054 {\n" + "> -\t\tahb1: ahb1_clk@01c20054 {\n" "> -\t\t\t#clock-cells = <0>;\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" "> -\t\t\treg = <0x01c20054 0x4>;\n" @@ -216,7 +227,7 @@ "> -\t\t\tclock-output-names = \"ahb1\";\n" "> -\t\t};\n" "> -\n" - "> -\t\tapb1: apb1_clk at 01c20054 {\n" + "> -\t\tapb1: apb1_clk@01c20054 {\n" "> -\t\t\t#clock-cells = <0>;\n" "> -\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n" "> -\t\t\treg = <0x01c20054 0x4>;\n" @@ -224,14 +235,14 @@ "> -\t\t\tclock-output-names = \"apb1\";\n" "> -\t\t};\n" "> -\n" - "> \t\tahb1_gates: clk at 01c20060 {\n" + "> \t\tahb1_gates: clk@01c20060 {\n" "> \t\t\t#clock-cells = <1>;\n" "> \t\t\tcompatible = \"allwinner,sun8i-a23-ahb1-gates-clk\";\n" "> @@ -228,36 +129,6 @@\n" "> \t\t\t\t\t\"apb2_uart3\", \"apb2_uart4\";\n" "> \t\t};\n" "> \n" - "> -\t\tmmc0_clk: clk at 01c20088 {\n" + "> -\t\tmmc0_clk: clk@01c20088 {\n" "> -\t\t\t#clock-cells = <1>;\n" "> -\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> -\t\t\treg = <0x01c20088 0x4>;\n" @@ -241,7 +252,7 @@ "> -\t\t\t\t\t \"mmc0_sample\";\n" "> -\t\t};\n" "> -\n" - "> -\t\tmmc1_clk: clk at 01c2008c {\n" + "> -\t\tmmc1_clk: clk@01c2008c {\n" "> -\t\t\t#clock-cells = <1>;\n" "> -\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> -\t\t\treg = <0x01c2008c 0x4>;\n" @@ -251,7 +262,7 @@ "> -\t\t\t\t\t \"mmc1_sample\";\n" "> -\t\t};\n" "> -\n" - "> -\t\tmmc2_clk: clk at 01c20090 {\n" + "> -\t\tmmc2_clk: clk@01c20090 {\n" "> -\t\t\t#clock-cells = <1>;\n" "> -\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> -\t\t\treg = <0x01c20090 0x4>;\n" @@ -261,26 +272,26 @@ "> -\t\t\t\t\t \"mmc2_sample\";\n" "> -\t\t};\n" "> -\n" - "> \t\tmbus_clk: clk at 01c2015c {\n" + "> \t\tmbus_clk: clk@01c2015c {\n" "> \t\t\t#clock-cells = <0>;\n" "> \t\t\tcompatible = \"allwinner,sun8i-a23-mbus-clk\";\n" "> @@ -268,11 +139,6 @@\n" "> \t};\n" "> \n" - "> \tsoc at 01c00000 {\n" + "> \tsoc@01c00000 {\n" "> -\t\tcompatible = \"simple-bus\";\n" "> -\t\t#address-cells = <1>;\n" "> -\t\t#size-cells = <1>;\n" "> -\t\tranges;\n" "> -\n" - "> \t\tdma: dma-controller at 01c02000 {\n" + "> \t\tdma: dma-controller@01c02000 {\n" "> \t\t\tcompatible = \"allwinner,sun8i-a23-dma\";\n" "> \t\t\treg = <0x01c02000 0x1000>;\n" "> @@ -282,75 +148,12 @@\n" "> \t\t\t#dma-cells = <1>;\n" "> \t\t};\n" "> \n" - "> -\t\tmmc0: mmc at 01c0f000 {\n" + "> -\t\tmmc0: mmc@01c0f000 {\n" "> -\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> -\t\t\treg = <0x01c0f000 0x1000>;\n" "> -\t\t\tclocks = <&ahb1_gates 8>,\n" @@ -299,7 +310,7 @@ "> -\t\t\t#size-cells = <0>;\n" "> -\t\t};\n" "> -\n" - "> -\t\tmmc1: mmc at 01c10000 {\n" + "> -\t\tmmc1: mmc@01c10000 {\n" "> -\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> -\t\t\treg = <0x01c10000 0x1000>;\n" "> -\t\t\tclocks = <&ahb1_gates 9>,\n" @@ -318,7 +329,7 @@ "> -\t\t\t#size-cells = <0>;\n" "> -\t\t};\n" "> -\n" - "> -\t\tmmc2: mmc at 01c11000 {\n" + "> -\t\tmmc2: mmc@01c11000 {\n" "> -\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> -\t\t\treg = <0x01c11000 0x1000>;\n" "> -\t\t\tclocks = <&ahb1_gates 10>,\n" @@ -337,7 +348,7 @@ "> -\t\t\t#size-cells = <0>;\n" "> -\t\t};\n" "> -\n" - "> \t\tpio: pinctrl at 01c20800 {\n" + "> \t\tpio: pinctrl@01c20800 {\n" "> \t\t\tcompatible = \"allwinner,sun8i-a23-pinctrl\";\n" "> -\t\t\treg = <0x01c20800 0x400>;\n" "> \t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -351,52 +362,52 @@ "> -\t\t\t#gpio-cells = <3>;\n" "> +\n" "> \n" - "> \t\t\tuart0_pins_a: uart0 at 0 {\n" + "> \t\t\tuart0_pins_a: uart0@0 {\n" "> \t\t\t\tallwinner,pins = \"PF2\", \"PF4\";\n" "> @@ -359,20 +162,6 @@\n" "> \t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> \t\t\t};\n" "> \n" - "> -\t\t\tmmc0_pins_a: mmc0 at 0 {\n" + "> -\t\t\tmmc0_pins_a: mmc0@0 {\n" "> -\t\t\t\tallwinner,pins = \"PF0\",\"PF1\",\"PF2\",\"PF3\",\"PF4\",\"PF5\";\n" "> -\t\t\t\tallwinner,function = \"mmc0\";\n" "> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n" "> -\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> -\t\t\t};\n" "> -\n" - "> -\t\t\tmmc1_pins_a: mmc1 at 0 {\n" + "> -\t\t\tmmc1_pins_a: mmc1@0 {\n" "> -\t\t\t\tallwinner,pins = \"PG0\",\"PG1\",\"PG2\",\"PG3\",\"PG4\",\"PG5\";\n" "> -\t\t\t\tallwinner,function = \"mmc1\";\n" "> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n" "> -\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> -\t\t\t};\n" "> -\n" - "> \t\t\ti2c0_pins_a: i2c0 at 0 {\n" + "> \t\t\ti2c0_pins_a: i2c0@0 {\n" "> \t\t\t\tallwinner,pins = \"PH2\", \"PH3\";\n" "> \t\t\t\tallwinner,function = \"i2c0\";\n" "> @@ -395,38 +184,6 @@\n" "> \t\t\t};\n" "> \t\t};\n" "> \n" - "> -\t\tahb1_rst: reset at 01c202c0 {\n" + "> -\t\tahb1_rst: reset@01c202c0 {\n" "> -\t\t\t#reset-cells = <1>;\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> -\t\t\treg = <0x01c202c0 0xc>;\n" "> -\t\t};\n" "> -\n" - "> -\t\tapb1_rst: reset at 01c202d0 {\n" + "> -\t\tapb1_rst: reset@01c202d0 {\n" "> -\t\t\t#reset-cells = <1>;\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> -\t\t\treg = <0x01c202d0 0x4>;\n" "> -\t\t};\n" "> -\n" - "> -\t\tapb2_rst: reset at 01c202d8 {\n" + "> -\t\tapb2_rst: reset@01c202d8 {\n" "> -\t\t\t#reset-cells = <1>;\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> -\t\t\treg = <0x01c202d8 0x4>;\n" "> -\t\t};\n" "> -\n" - "> -\t\ttimer at 01c20c00 {\n" + "> -\t\ttimer@01c20c00 {\n" "> -\t\t\tcompatible = \"allwinner,sun4i-a10-timer\";\n" "> -\t\t\treg = <0x01c20c00 0xa0>;\n" "> -\t\t\tinterrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -404,20 +415,20 @@ "> -\t\t\tclocks = <&osc24M>;\n" "> -\t\t};\n" "> -\n" - "> -\t\twdt0: watchdog at 01c20ca0 {\n" + "> -\t\twdt0: watchdog@01c20ca0 {\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-wdt\";\n" "> -\t\t\treg = <0x01c20ca0 0x20>;\n" "> -\t\t\tinterrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;\n" "> -\t\t};\n" "> -\n" - "> \t\tlradc: lradc at 01c22800 {\n" + "> \t\tlradc: lradc@01c22800 {\n" "> \t\t\tcompatible = \"allwinner,sun4i-a10-lradc-keys\";\n" "> \t\t\treg = <0x01c22800 0x100>;\n" "> @@ -434,58 +191,6 @@\n" "> \t\t\tstatus = \"disabled\";\n" "> \t\t};\n" "> \n" - "> -\t\tuart0: serial at 01c28000 {\n" + "> -\t\tuart0: serial@01c28000 {\n" "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> -\t\t\treg = <0x01c28000 0x400>;\n" "> -\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -430,7 +441,7 @@ "> -\t\t\tstatus = \"disabled\";\n" "> -\t\t};\n" "> -\n" - "> -\t\tuart1: serial at 01c28400 {\n" + "> -\t\tuart1: serial@01c28400 {\n" "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> -\t\t\treg = <0x01c28400 0x400>;\n" "> -\t\t\tinterrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -443,7 +454,7 @@ "> -\t\t\tstatus = \"disabled\";\n" "> -\t\t};\n" "> -\n" - "> -\t\tuart2: serial at 01c28800 {\n" + "> -\t\tuart2: serial@01c28800 {\n" "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> -\t\t\treg = <0x01c28800 0x400>;\n" "> -\t\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -456,7 +467,7 @@ "> -\t\t\tstatus = \"disabled\";\n" "> -\t\t};\n" "> -\n" - "> -\t\tuart3: serial at 01c28c00 {\n" + "> -\t\tuart3: serial@01c28c00 {\n" "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> -\t\t\treg = <0x01c28c00 0x400>;\n" "> -\t\t\tinterrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -469,7 +480,7 @@ "> -\t\t\tstatus = \"disabled\";\n" "> -\t\t};\n" "> -\n" - "> \t\tuart4: serial at 01c29000 {\n" + "> \t\tuart4: serial@01c29000 {\n" "> \t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> \t\t\treg = <0x01c29000 0x400>;\n" "> @@ -498,136 +203,5 @@\n" @@ -477,7 +488,7 @@ "> \t\t\tstatus = \"disabled\";\n" "> \t\t};\n" "> -\n" - "> -\t\ti2c0: i2c at 01c2ac00 {\n" + "> -\t\ti2c0: i2c@01c2ac00 {\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n" "> -\t\t\treg = <0x01c2ac00 0x400>;\n" "> -\t\t\tinterrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -488,7 +499,7 @@ "> -\t\t\t#size-cells = <0>;\n" "> -\t\t};\n" "> -\n" - "> -\t\ti2c1: i2c at 01c2b000 {\n" + "> -\t\ti2c1: i2c@01c2b000 {\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n" "> -\t\t\treg = <0x01c2b000 0x400>;\n" "> -\t\t\tinterrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -499,7 +510,7 @@ "> -\t\t\t#size-cells = <0>;\n" "> -\t\t};\n" "> -\n" - "> -\t\ti2c2: i2c at 01c2b400 {\n" + "> -\t\ti2c2: i2c@01c2b400 {\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n" "> -\t\t\treg = <0x01c2b400 0x400>;\n" "> -\t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -510,7 +521,7 @@ "> -\t\t\t#size-cells = <0>;\n" "> -\t\t};\n" "> -\n" - "> -\t\tgic: interrupt-controller at 01c81000 {\n" + "> -\t\tgic: interrupt-controller@01c81000 {\n" "> -\t\t\tcompatible = \"arm,cortex-a7-gic\", \"arm,cortex-a15-gic\";\n" "> -\t\t\treg = <0x01c81000 0x1000>,\n" "> -\t\t\t <0x01c82000 0x1000>,\n" @@ -521,14 +532,14 @@ "> -\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" "> -\t\t};\n" "> -\n" - "> -\t\trtc: rtc at 01f00000 {\n" + "> -\t\trtc: rtc@01f00000 {\n" "> -\t\t\tcompatible = \"allwinner,sun6i-a31-rtc\";\n" "> -\t\t\treg = <0x01f00000 0x54>;\n" "> -\t\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,\n" "> -\t\t\t\t <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;\n" "> -\t\t};\n" "> -\n" - "> -\t\tprcm at 01f01400 {\n" + "> -\t\tprcm@01f01400 {\n" "> -\t\t\tcompatible = \"allwinner,sun8i-a23-prcm\";\n" "> -\t\t\treg = <0x01f01400 0x200>;\n" "> -\n" @@ -572,12 +583,12 @@ "> -\t\t\t};\n" "> -\t\t};\n" "> -\n" - "> -\t\tcpucfg at 01f01c00 {\n" + "> -\t\tcpucfg@01f01c00 {\n" "> -\t\t\tcompatible = \"allwinner,sun8i-a23-cpuconfig\";\n" "> -\t\t\treg = <0x01f01c00 0x300>;\n" "> -\t\t};\n" "> -\n" - "> -\t\tr_uart: serial at 01f02800 {\n" + "> -\t\tr_uart: serial@01f02800 {\n" "> -\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> -\t\t\treg = <0x01f02800 0x400>;\n" "> -\t\t\tinterrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -588,7 +599,7 @@ "> -\t\t\tstatus = \"disabled\";\n" "> -\t\t};\n" "> -\n" - "> -\t\tr_pio: pinctrl at 01f02c00 {\n" + "> -\t\tr_pio: pinctrl@01f02c00 {\n" "> -\t\t\tcompatible = \"allwinner,sun8i-a23-r-pinctrl\";\n" "> -\t\t\treg = <0x01f02c00 0x400>;\n" "> -\t\t\tinterrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -600,7 +611,7 @@ "> -\t\t\t#size-cells = <0>;\n" "> -\t\t\t#gpio-cells = <3>;\n" "> -\n" - "> -\t\t\tr_uart_pins_a: r_uart at 0 {\n" + "> -\t\t\tr_uart_pins_a: r_uart@0 {\n" "> -\t\t\t\tallwinner,pins = \"PL2\", \"PL3\";\n" "> -\t\t\t\tallwinner,function = \"s_uart\";\n" "> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" @@ -674,7 +685,7 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tframebuffer at 0 {\n" + "> +\t\tframebuffer@0 {\n" "> +\t\t\tcompatible = \"allwinner,simple-framebuffer\",\n" "> +\t\t\t\t \"simple-framebuffer\";\n" "> +\t\t\tallwinner,pipeline = \"de_be0-lcd0\";\n" @@ -712,7 +723,7 @@ "> +\t\t\tclock-output-names = \"osc32k\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll1: clk at 01c20000 {\n" + "> +\t\tpll1: clk@01c20000 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n" "> +\t\t\treg = <0x01c20000 0x4>;\n" @@ -720,7 +731,7 @@ "> +\t\t\tclock-output-names = \"pll1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll6: clk at 01c20028 {\n" + "> +\t\tpll6: clk@01c20028 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" "> +\t\t\treg = <0x01c20028 0x4>;\n" @@ -728,7 +739,7 @@ "> +\t\t\tclock-output-names = \"pll6\", \"pll6x2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu: cpu_clk at 01c20050 {\n" + "> +\t\tcpu: cpu_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -744,7 +755,7 @@ "> +\t\t};\n" "> +\n" "> +\n" - "> +\t\tahb1: ahb1_clk at 01c20054 {\n" + "> +\t\tahb1: ahb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -752,7 +763,7 @@ "> +\t\t\tclock-output-names = \"ahb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb1: apb1_clk at 01c20054 {\n" + "> +\t\tapb1: apb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -760,7 +771,7 @@ "> +\t\t\tclock-output-names = \"apb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc0_clk: clk at 01c20088 {\n" + "> +\t\tmmc0_clk: clk@01c20088 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c20088 0x4>;\n" @@ -770,7 +781,7 @@ "> +\t\t\t\t\t \"mmc0_sample\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc1_clk: clk at 01c2008c {\n" + "> +\t\tmmc1_clk: clk@01c2008c {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c2008c 0x4>;\n" @@ -780,7 +791,7 @@ "> +\t\t\t\t\t \"mmc1_sample\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc2_clk: clk at 01c20090 {\n" + "> +\t\tmmc2_clk: clk@01c20090 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c20090 0x4>;\n" @@ -792,14 +803,14 @@ "> +\n" "> +\t};\n" "> +\n" - "> +\tsoc at 01c00000 {\n" + "> +\tsoc@01c00000 {\n" "> +\t\tcompatible = \"simple-bus\";\n" "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" "> +\n" - "> +\t\tmmc0: mmc at 01c0f000 {\n" + "> +\t\tmmc0: mmc@01c0f000 {\n" "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c0f000 0x1000>;\n" "> +\t\t\tclocks = <&ahb1_gates 8>,\n" @@ -818,7 +829,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc1: mmc at 01c10000 {\n" + "> +\t\tmmc1: mmc@01c10000 {\n" "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c10000 0x1000>;\n" "> +\t\t\tclocks = <&ahb1_gates 9>,\n" @@ -837,7 +848,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc2: mmc at 01c11000 {\n" + "> +\t\tmmc2: mmc@01c11000 {\n" "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c11000 0x1000>;\n" "> +\t\t\tclocks = <&ahb1_gates 10>,\n" @@ -856,7 +867,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tpio: pinctrl at 01c20800 {\n" + "> +\t\tpio: pinctrl@01c20800 {\n" "> +\t\t\treg = <0x01c20800 0x400>;\n" "> +\t\t\tclocks = <&apb1_gates 5>;\n" "> +\t\t\tgpio-controller;\n" @@ -865,14 +876,14 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t\t#gpio-cells = <3>;\n" "> +\n" - "> +\t\t\tmmc0_pins_a: mmc0 at 0 {\n" + "> +\t\t\tmmc0_pins_a: mmc0@0 {\n" "> +\t\t\t\tallwinner,pins = \"PF0\",\"PF1\",\"PF2\",\"PF3\",\"PF4\",\"PF5\";\n" "> +\t\t\t\tallwinner,function = \"mmc0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc1_pins_a: mmc1 at 0 {\n" + "> +\t\t\tmmc1_pins_a: mmc1@0 {\n" "> +\t\t\t\tallwinner,pins = \"PG0\",\"PG1\",\"PG2\",\"PG3\",\"PG4\",\"PG5\";\n" "> +\t\t\t\tallwinner,function = \"mmc1\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n" @@ -880,25 +891,25 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb1_rst: reset at 01c202c0 {\n" + "> +\t\tahb1_rst: reset@01c202c0 {\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> +\t\t\treg = <0x01c202c0 0xc>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb1_rst: reset at 01c202d0 {\n" + "> +\t\tapb1_rst: reset@01c202d0 {\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> +\t\t\treg = <0x01c202d0 0x4>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb2_rst: reset at 01c202d8 {\n" + "> +\t\tapb2_rst: reset@01c202d8 {\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> +\t\t\treg = <0x01c202d8 0x4>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ttimer at 01c20c00 {\n" + "> +\t\ttimer@01c20c00 {\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-timer\";\n" "> +\t\t\treg = <0x01c20c00 0xa0>;\n" "> +\t\t\tinterrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -906,13 +917,13 @@ "> +\t\t\tclocks = <&osc24M>;\n" "> +\t\t};\n" "> +\n" - "> +\t\twdt0: watchdog at 01c20ca0 {\n" + "> +\t\twdt0: watchdog@01c20ca0 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-wdt\";\n" "> +\t\t\treg = <0x01c20ca0 0x20>;\n" "> +\t\t\tinterrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart0: serial at 01c28000 {\n" + "> +\t\tuart0: serial@01c28000 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -925,7 +936,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart1: serial at 01c28400 {\n" + "> +\t\tuart1: serial@01c28400 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28400 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -938,7 +949,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart2: serial at 01c28800 {\n" + "> +\t\tuart2: serial@01c28800 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28800 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -951,7 +962,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart3: serial at 01c28c00 {\n" + "> +\t\tuart3: serial@01c28c00 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28c00 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -964,7 +975,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c0: i2c at 01c2ac00 {\n" + "> +\t\ti2c0: i2c@01c2ac00 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n" "> +\t\t\treg = <0x01c2ac00 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -975,7 +986,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c1: i2c at 01c2b000 {\n" + "> +\t\ti2c1: i2c@01c2b000 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n" "> +\t\t\treg = <0x01c2b000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -986,7 +997,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c2: i2c at 01c2b400 {\n" + "> +\t\ti2c2: i2c@01c2b400 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n" "> +\t\t\treg = <0x01c2b400 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -997,7 +1008,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgic: interrupt-controller at 01c81000 {\n" + "> +\t\tgic: interrupt-controller@01c81000 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7-gic\", \"arm,cortex-a15-gic\";\n" "> +\t\t\treg = <0x01c81000 0x1000>,\n" "> +\t\t\t <0x01c82000 0x1000>,\n" @@ -1008,14 +1019,14 @@ "> +\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" "> +\t\t};\n" "> +\n" - "> +\t\trtc: rtc at 01f00000 {\n" + "> +\t\trtc: rtc@01f00000 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-rtc\";\n" "> +\t\t\treg = <0x01f00000 0x54>;\n" "> +\t\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,\n" "> +\t\t\t\t <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tprcm at 01f01400 {\n" + "> +\t\tprcm@01f01400 {\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-prcm\";\n" "> +\t\t\treg = <0x01f01400 0x200>;\n" "> +\n" @@ -1059,12 +1070,12 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpucfg at 01f01c00 {\n" + "> +\t\tcpucfg@01f01c00 {\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-cpuconfig\";\n" "> +\t\t\treg = <0x01f01c00 0x300>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tr_uart: serial at 01f02800 {\n" + "> +\t\tr_uart: serial@01f02800 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01f02800 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -1075,7 +1086,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tr_pio: pinctrl at 01f02c00 {\n" + "> +\t\tr_pio: pinctrl@01f02c00 {\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-r-pinctrl\";\n" "> +\t\t\treg = <0x01f02c00 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -1087,7 +1098,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t\t#gpio-cells = <3>;\n" "> +\n" - "> +\t\t\tr_uart_pins_a: r_uart at 0 {\n" + "> +\t\t\tr_uart_pins_a: r_uart@0 {\n" "> +\t\t\t\tallwinner,pins = \"PL2\", \"PL3\";\n" "> +\t\t\t\tallwinner,function = \"s_uart\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" @@ -1117,13 +1128,27 @@ "-- \n" "Maxime Ripard, Free Electrons\n" "Embedded Linux, Kernel and Android engineering\n" - "http://free-electrons.com\n" - "-------------- next part --------------\n" - "A non-text attachment was scrubbed...\n" - "Name: signature.asc\n" - "Type: application/pgp-signature\n" - "Size: 819 bytes\n" - "Desc: Digital signature\n" - URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20150510/1821ffb1/attachment-0001.sig> + http://free-electrons.com + "\01:2\0" + "fn\0signature.asc\0" + "d\0Digital signature\0" + "b\0" + "-----BEGIN PGP SIGNATURE-----\n" + "Version: GnuPG v1\n" + "\n" + "iQIcBAEBAgAGBQJVTzXRAAoJEBx+YmzsjxAgj8gQAJuO0eGtdyu+LSp12avsPtwt\n" + "8qx8GiJ9JM5zJHL2vrLTfW2ntsYUCDU9b+Z02oevo59giYrBWNSzvkUgsu1RQE0U\n" + "jrxhL7XuWSXfUXeF4IsnqpZhLStacT+RlZg0H+SDc6hBATO1P42JAwQ8zHRW5UwK\n" + "xOimGaMtpJ2fYF8kwUgOEB3/N4BMmelQ6K4YPtqlmpB6RjZzZ1uYaRDGtFPztJOP\n" + "zhqwrQUXv28yVO8HybPSSTZwReparWZyOjn5QS2OpxL91mni0xkoTumPdjOonlKi\n" + "Gf7Lc6J+esog4NyqGxjrNZUww26Z6KlL5ehkqfVpYDoPTZ/Yhe6jrewx6cL1cjVT\n" + "A5/GOubBkPaVV+DfwAiTBTDVrhilOrn2sKKTqVQ4mPbLz49ufImQcwQw5s7kocar\n" + "Vko6+dZfyTPz9eh0EsMMvJ53PJRrrMSWxhSw+h5EH6Knq2f/E/AU9BbYzhcXW3yB\n" + "cgv8FzMW/5S7zgo7M2V9ay7YCPjGNuo7SHGdqR/3JWWcHYhWa+dP8cR7HW15u0mC\n" + "/0n1MfTG/Dfk25Ae2WVaf6cJep0M7k3PZyuYkLzvk8J0EatVb/8DM5DxwRvsPR26\n" + "pQL+DQg9n7PQ5EE4SDV+A4/qxaIdeih9hOru4Fwiyb/kXpuAlaRrst9qxswLTK4b\n" + "7hGPAc6Yh+zprvr6WFM+\n" + "=2bSM\n" + "-----END PGP SIGNATURE-----\n" -dc4a2086779727b08c61f9b0bfa11fb002b61355f7c8f0000e18edbba96e1955 +0744b0af8794445f1e4b6b3bff14a266f765439ab17a0070fdaa3e620974d90c
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.