diff for duplicates of <20150512221202.16410.2827@quantum> diff --git a/a/1.txt b/N1/1.txt index 4dc523b..5402f07 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,18 +1,13 @@ Quoting Joachim Eastwood (2015-04-27 14:38:11) > Add DT binding documentation for lpc1850-cgu driver. -> = - +> > Signed-off-by: Joachim Eastwood <manabian@gmail.com> > --- -> .../devicetree/bindings/clock/lpc1850-cgu.txt | 138 +++++++++++++++= -++++++ +> .../devicetree/bindings/clock/lpc1850-cgu.txt | 138 +++++++++++++++++++++ > 1 file changed, 138 insertions(+) -> create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-cgu.t= -xt -> = - -> diff --git a/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt b/Do= -cumentation/devicetree/bindings/clock/lpc1850-cgu.txt +> create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-cgu.txt +> +> diff --git a/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt b/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt > new file mode 100644 > index 000000000000..0b278ca6aee7 > --- /dev/null @@ -65,27 +60,19 @@ s/cloks/clocks/ > + > +Number: Name: Description: -> + 0 BASE_SAFE_CLK Base safe clock (always on) for W= -WDT +> + 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT > + 1 BASE_USB0_CLK Base clock for USB0 -> + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsy= -stem, +> + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem, > + SPI, and SGPIO > + 3 BASE_USB1_CLK Base clock for USB1 -> + 4 BASE_CPU_CLK System base clock for ARM Cortex-= -M core -> + and APB peripheral blocks #0 and = -#2 +> + 4 BASE_CPU_CLK System base clock for ARM Cortex-M core +> + and APB peripheral blocks #0 and #2 > + 5 BASE_SPIFI_CLK Base clock for SPIFI > + 6 BASE_SPI_CLK Base clock for SPI -> + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Recei= -ve clock -> + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Trans= -mit clock -> + 9 BASE_APB1_CLK Base clock for APB peripheral blo= -ck # 1 -> +10 BASE_APB3_CLK Base clock for APB peripheral blo= -ck # 3 +> + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock +> + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock +> + 9 BASE_APB1_CLK Base clock for APB peripheral block # 1 +> +10 BASE_APB3_CLK Base clock for APB peripheral block # 3 > +11 BASE_LCD_CLK Base clock for LCD > +12 BASE_ADCHS_CLK Base clock for ADCHS > +13 BASE_SDIO_CLK Base clock for SD/MMC @@ -98,10 +85,8 @@ ck # 3 > +20 BASE_OUT_CLK Base clock for CLKOUT pin > +24-21 - Reserved > +25 BASE_AUDIO_CLK Base clock for audio system (I2S) -> +26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock out= -put -> +27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock out= -put +> +26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output +> +27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output > + > +BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx. > +BASE_ADCHS_CLK is only available on LPC4370. @@ -112,76 +97,60 @@ put > +/ { > + clocks { > + xtal: xtal { -> + compatible =3D "fixed-clock"; -> + #clock-cells =3D <0>; -> + clock-frequency =3D <12000000>; +> + compatible = "fixed-clock"; +> + #clock-cells = <0>; +> + clock-frequency = <12000000>; > + }; > + > + xtal32: xtal32 { -> + compatible =3D "fixed-clock"; -> + #clock-cells =3D <0>; -> + clock-frequency =3D <32768>; +> + compatible = "fixed-clock"; +> + #clock-cells = <0>; +> + clock-frequency = <32768>; > + }; > + > + enet_rx_clk: enet_rx_clk { -> + compatible =3D "fixed-clock"; -> + #clock-cells =3D <0>; -> + clock-frequency =3D <0>; -> + clock-output-names =3D "enet_rx_clk"; +> + compatible = "fixed-clock"; +> + #clock-cells = <0>; +> + clock-frequency = <0>; +> + clock-output-names = "enet_rx_clk"; > + }; > + > + enet_tx_clk: enet_tx_clk { -> + compatible =3D "fixed-clock"; -> + #clock-cells =3D <0>; -> + clock-frequency =3D <0>; -> + clock-output-names =3D "enet_tx_clk"; +> + compatible = "fixed-clock"; +> + #clock-cells = <0>; +> + clock-frequency = <0>; +> + clock-output-names = "enet_tx_clk"; > + }; > + > + gp_clkin: gp_clkin { -> + compatible =3D "fixed-clock"; -> + #clock-cells =3D <0>; -> + clock-frequency =3D <0>; -> + clock-output-names =3D "gp_clkin"; +> + compatible = "fixed-clock"; +> + #clock-cells = <0>; +> + clock-frequency = <0>; +> + clock-output-names = "gp_clkin"; > + }; > + }; > + > + soc { -> + cgu: cgu@40050000 { -> + compatible =3D "nxp,lpc1850-cgu"; -> + reg =3D <0x40050000 0x1000>; -> + #clock-cells =3D <1>; -> + clocks =3D <&xtal>, <&creg_clk 1>, <&enet_rx_clk>= -, <&enet_tx_clk>, <&gp_clkin>; -> + clock-indices =3D <0>, <1>, <2>, <3>, <4>, = -<5>, <6>, <7>, -> + <8>, <9>, <10>, <11>, <12>, <13= ->, <14>, <15>, -> + <16>, <17>, <18>, <19>, <20>, <25= ->, <26>, <27>; -> + clock-output-names =3D "base_safe_clk", "base_= -usb0_clk", -> + "base_periph_clk", "base_us= -b1_clk", -> + "base_cpu_clk", "base_sp= -ifi_clk", -> + "base_spi_clk", "base_ph= -y_rx_clk", -> + "base_phy_tx_clk", "base_ap= -b1_clk", -> + "base_apb3_clk", "base_lc= -d_clk", -> + "base_adchs_clk", "base_sd= -io_clk", -> + "base_ssp0_clk", "base_ss= -p1_clk", -> + "base_uart0_clk", "base_ua= -rt1_clk", -> + "base_uart2_clk", "base_ua= -rt3_clk", -> + "base_out_clk", "base_au= -dio_clk", -> + "base_cgu_out0_clk","base_cg= -u_out1_clk"; +> + cgu: cgu at 40050000 { +> + compatible = "nxp,lpc1850-cgu"; +> + reg = <0x40050000 0x1000>; +> + #clock-cells = <1>; +> + clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; +> + clock-indices = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, +> + <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, +> + <16>, <17>, <18>, <19>, <20>, <25>, <26>, <27>; +> + clock-output-names = "base_safe_clk", "base_usb0_clk", +> + "base_periph_clk", "base_usb1_clk", +> + "base_cpu_clk", "base_spifi_clk", +> + "base_spi_clk", "base_phy_rx_clk", +> + "base_phy_tx_clk", "base_apb1_clk", +> + "base_apb3_clk", "base_lcd_clk", +> + "base_adchs_clk", "base_sdio_clk", +> + "base_ssp0_clk", "base_ssp1_clk", +> + "base_uart0_clk", "base_uart1_clk", +> + "base_uart2_clk", "base_uart3_clk", +> + "base_out_clk", "base_audio_clk", +> + "base_cgu_out0_clk","base_cgu_out1_clk"; Why do you need to use clock-indices? @@ -199,7 +168,6 @@ Mike > + }; > + }; > +}; -> -- = - +> -- > 1.8.0 ->=20 +> diff --git a/a/content_digest b/N1/content_digest index 5ed4b61..3df04db 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,34 +1,21 @@ "ref\01430170693-28303-1-git-send-email-manabian@gmail.com\0" "ref\01430170693-28303-3-git-send-email-manabian@gmail.com\0" - "From\0Michael Turquette <mturquette@linaro.org>\0" - "Subject\0Re: [PATCH v2 2/4] doc: dt: add documentation for lpc1850-cgu clk driver\0" + "From\0mturquette@linaro.org (Michael Turquette)\0" + "Subject\0[PATCH v2 2/4] doc: dt: add documentation for lpc1850-cgu clk driver\0" "Date\0Tue, 12 May 2015 15:12:02 -0700\0" - "To\0Joachim Eastwood <manabian@gmail.com>" - sboyd@codeaurora.org - arnd@arndb.de - linux-clk@vger.kernel.org - " linux-arm-kernel@lists.infradead.org\0" - "Cc\0devicetree@vger.kernel.org" - ariel.dalessandro@gmail.com - ezequiel@vanguardiasur.com.ar - " Joachim Eastwood <manabian@gmail.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Quoting Joachim Eastwood (2015-04-27 14:38:11)\n" "> Add DT binding documentation for lpc1850-cgu driver.\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Joachim Eastwood <manabian@gmail.com>\n" "> ---\n" - "> .../devicetree/bindings/clock/lpc1850-cgu.txt | 138 +++++++++++++++=\n" - "++++++\n" + "> .../devicetree/bindings/clock/lpc1850-cgu.txt | 138 +++++++++++++++++++++\n" "> 1 file changed, 138 insertions(+)\n" - "> create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-cgu.t=\n" - "xt\n" - "> =\n" - "\n" - "> diff --git a/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt b/Do=\n" - "cumentation/devicetree/bindings/clock/lpc1850-cgu.txt\n" + "> create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-cgu.txt\n" + "> \n" + "> diff --git a/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt b/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt\n" "> new file mode 100644\n" "> index 000000000000..0b278ca6aee7\n" "> --- /dev/null\n" @@ -81,27 +68,19 @@ "\n" "> +\n" "> +Number: Name: Description:\n" - "> + 0 BASE_SAFE_CLK Base safe clock (always on) for W=\n" - "WDT\n" + "> + 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT\n" "> + 1 BASE_USB0_CLK Base clock for USB0\n" - "> + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsy=\n" - "stem,\n" + "> + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem,\n" "> + SPI, and SGPIO\n" "> + 3 BASE_USB1_CLK Base clock for USB1\n" - "> + 4 BASE_CPU_CLK System base clock for ARM Cortex-=\n" - "M core\n" - "> + and APB peripheral blocks #0 and =\n" - "#2\n" + "> + 4 BASE_CPU_CLK System base clock for ARM Cortex-M core\n" + "> + and APB peripheral blocks #0 and #2\n" "> + 5 BASE_SPIFI_CLK Base clock for SPIFI\n" "> + 6 BASE_SPI_CLK Base clock for SPI\n" - "> + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Recei=\n" - "ve clock\n" - "> + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Trans=\n" - "mit clock\n" - "> + 9 BASE_APB1_CLK Base clock for APB peripheral blo=\n" - "ck # 1\n" - "> +10 BASE_APB3_CLK Base clock for APB peripheral blo=\n" - "ck # 3\n" + "> + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock\n" + "> + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock\n" + "> + 9 BASE_APB1_CLK Base clock for APB peripheral block # 1\n" + "> +10 BASE_APB3_CLK Base clock for APB peripheral block # 3\n" "> +11 BASE_LCD_CLK Base clock for LCD\n" "> +12 BASE_ADCHS_CLK Base clock for ADCHS\n" "> +13 BASE_SDIO_CLK Base clock for SD/MMC\n" @@ -114,10 +93,8 @@ "> +20 BASE_OUT_CLK Base clock for CLKOUT pin\n" "> +24-21 - Reserved\n" "> +25 BASE_AUDIO_CLK Base clock for audio system (I2S)\n" - "> +26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock out=\n" - "put\n" - "> +27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock out=\n" - "put\n" + "> +26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output\n" + "> +27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output\n" "> +\n" "> +BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx.\n" "> +BASE_ADCHS_CLK is only available on LPC4370.\n" @@ -128,76 +105,60 @@ "> +/ {\n" "> + clocks {\n" "> + xtal: xtal {\n" - "> + compatible =3D \"fixed-clock\";\n" - "> + #clock-cells =3D <0>;\n" - "> + clock-frequency =3D <12000000>;\n" + "> + compatible = \"fixed-clock\";\n" + "> + #clock-cells = <0>;\n" + "> + clock-frequency = <12000000>;\n" "> + };\n" "> +\n" "> + xtal32: xtal32 {\n" - "> + compatible =3D \"fixed-clock\";\n" - "> + #clock-cells =3D <0>;\n" - "> + clock-frequency =3D <32768>;\n" + "> + compatible = \"fixed-clock\";\n" + "> + #clock-cells = <0>;\n" + "> + clock-frequency = <32768>;\n" "> + };\n" "> +\n" "> + enet_rx_clk: enet_rx_clk {\n" - "> + compatible =3D \"fixed-clock\";\n" - "> + #clock-cells =3D <0>;\n" - "> + clock-frequency =3D <0>;\n" - "> + clock-output-names =3D \"enet_rx_clk\";\n" + "> + compatible = \"fixed-clock\";\n" + "> + #clock-cells = <0>;\n" + "> + clock-frequency = <0>;\n" + "> + clock-output-names = \"enet_rx_clk\";\n" "> + };\n" "> +\n" "> + enet_tx_clk: enet_tx_clk {\n" - "> + compatible =3D \"fixed-clock\";\n" - "> + #clock-cells =3D <0>;\n" - "> + clock-frequency =3D <0>;\n" - "> + clock-output-names =3D \"enet_tx_clk\";\n" + "> + compatible = \"fixed-clock\";\n" + "> + #clock-cells = <0>;\n" + "> + clock-frequency = <0>;\n" + "> + clock-output-names = \"enet_tx_clk\";\n" "> + };\n" "> +\n" "> + gp_clkin: gp_clkin {\n" - "> + compatible =3D \"fixed-clock\";\n" - "> + #clock-cells =3D <0>;\n" - "> + clock-frequency =3D <0>;\n" - "> + clock-output-names =3D \"gp_clkin\";\n" + "> + compatible = \"fixed-clock\";\n" + "> + #clock-cells = <0>;\n" + "> + clock-frequency = <0>;\n" + "> + clock-output-names = \"gp_clkin\";\n" "> + };\n" "> + };\n" "> +\n" "> + soc {\n" - "> + cgu: cgu@40050000 {\n" - "> + compatible =3D \"nxp,lpc1850-cgu\";\n" - "> + reg =3D <0x40050000 0x1000>;\n" - "> + #clock-cells =3D <1>;\n" - "> + clocks =3D <&xtal>, <&creg_clk 1>, <&enet_rx_clk>=\n" - ", <&enet_tx_clk>, <&gp_clkin>;\n" - "> + clock-indices =3D <0>, <1>, <2>, <3>, <4>, =\n" - "<5>, <6>, <7>,\n" - "> + <8>, <9>, <10>, <11>, <12>, <13=\n" - ">, <14>, <15>,\n" - "> + <16>, <17>, <18>, <19>, <20>, <25=\n" - ">, <26>, <27>;\n" - "> + clock-output-names =3D \"base_safe_clk\", \"base_=\n" - "usb0_clk\",\n" - "> + \"base_periph_clk\", \"base_us=\n" - "b1_clk\",\n" - "> + \"base_cpu_clk\", \"base_sp=\n" - "ifi_clk\",\n" - "> + \"base_spi_clk\", \"base_ph=\n" - "y_rx_clk\",\n" - "> + \"base_phy_tx_clk\", \"base_ap=\n" - "b1_clk\",\n" - "> + \"base_apb3_clk\", \"base_lc=\n" - "d_clk\",\n" - "> + \"base_adchs_clk\", \"base_sd=\n" - "io_clk\",\n" - "> + \"base_ssp0_clk\", \"base_ss=\n" - "p1_clk\",\n" - "> + \"base_uart0_clk\", \"base_ua=\n" - "rt1_clk\",\n" - "> + \"base_uart2_clk\", \"base_ua=\n" - "rt3_clk\",\n" - "> + \"base_out_clk\", \"base_au=\n" - "dio_clk\",\n" - "> + \"base_cgu_out0_clk\",\"base_cg=\n" - "u_out1_clk\";\n" + "> + cgu: cgu at 40050000 {\n" + "> + compatible = \"nxp,lpc1850-cgu\";\n" + "> + reg = <0x40050000 0x1000>;\n" + "> + #clock-cells = <1>;\n" + "> + clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;\n" + "> + clock-indices = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,\n" + "> + <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>,\n" + "> + <16>, <17>, <18>, <19>, <20>, <25>, <26>, <27>;\n" + "> + clock-output-names = \"base_safe_clk\", \"base_usb0_clk\",\n" + "> + \"base_periph_clk\", \"base_usb1_clk\",\n" + "> + \"base_cpu_clk\", \"base_spifi_clk\",\n" + "> + \"base_spi_clk\", \"base_phy_rx_clk\",\n" + "> + \"base_phy_tx_clk\", \"base_apb1_clk\",\n" + "> + \"base_apb3_clk\", \"base_lcd_clk\",\n" + "> + \"base_adchs_clk\", \"base_sdio_clk\",\n" + "> + \"base_ssp0_clk\", \"base_ssp1_clk\",\n" + "> + \"base_uart0_clk\", \"base_uart1_clk\",\n" + "> + \"base_uart2_clk\", \"base_uart3_clk\",\n" + "> + \"base_out_clk\", \"base_audio_clk\",\n" + "> + \"base_cgu_out0_clk\",\"base_cgu_out1_clk\";\n" "\n" "Why do you need to use clock-indices?\n" "\n" @@ -215,9 +176,8 @@ "> + };\n" "> + };\n" "> +};\n" - "> -- =\n" - "\n" + "> -- \n" "> 1.8.0\n" - >=20 + > -e56187fbba3cae487073dcea2674a8bf1a0b81a9a4197fb3ece60acebcac9cfb +41a917fed0366bf017f39979dbeea0b2f3f394afa214e86941115dfb193d5d52
diff --git a/a/1.txt b/N2/1.txt index 4dc523b..26e81f2 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,18 +1,13 @@ Quoting Joachim Eastwood (2015-04-27 14:38:11) > Add DT binding documentation for lpc1850-cgu driver. -> = - -> Signed-off-by: Joachim Eastwood <manabian@gmail.com> +> +> Signed-off-by: Joachim Eastwood <manabian-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > --- -> .../devicetree/bindings/clock/lpc1850-cgu.txt | 138 +++++++++++++++= -++++++ +> .../devicetree/bindings/clock/lpc1850-cgu.txt | 138 +++++++++++++++++++++ > 1 file changed, 138 insertions(+) -> create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-cgu.t= -xt -> = - -> diff --git a/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt b/Do= -cumentation/devicetree/bindings/clock/lpc1850-cgu.txt +> create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-cgu.txt +> +> diff --git a/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt b/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt > new file mode 100644 > index 000000000000..0b278ca6aee7 > --- /dev/null @@ -65,27 +60,19 @@ s/cloks/clocks/ > + > +Number: Name: Description: -> + 0 BASE_SAFE_CLK Base safe clock (always on) for W= -WDT +> + 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT > + 1 BASE_USB0_CLK Base clock for USB0 -> + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsy= -stem, +> + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem, > + SPI, and SGPIO > + 3 BASE_USB1_CLK Base clock for USB1 -> + 4 BASE_CPU_CLK System base clock for ARM Cortex-= -M core -> + and APB peripheral blocks #0 and = -#2 +> + 4 BASE_CPU_CLK System base clock for ARM Cortex-M core +> + and APB peripheral blocks #0 and #2 > + 5 BASE_SPIFI_CLK Base clock for SPIFI > + 6 BASE_SPI_CLK Base clock for SPI -> + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Recei= -ve clock -> + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Trans= -mit clock -> + 9 BASE_APB1_CLK Base clock for APB peripheral blo= -ck # 1 -> +10 BASE_APB3_CLK Base clock for APB peripheral blo= -ck # 3 +> + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock +> + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock +> + 9 BASE_APB1_CLK Base clock for APB peripheral block # 1 +> +10 BASE_APB3_CLK Base clock for APB peripheral block # 3 > +11 BASE_LCD_CLK Base clock for LCD > +12 BASE_ADCHS_CLK Base clock for ADCHS > +13 BASE_SDIO_CLK Base clock for SD/MMC @@ -98,10 +85,8 @@ ck # 3 > +20 BASE_OUT_CLK Base clock for CLKOUT pin > +24-21 - Reserved > +25 BASE_AUDIO_CLK Base clock for audio system (I2S) -> +26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock out= -put -> +27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock out= -put +> +26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output +> +27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output > + > +BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx. > +BASE_ADCHS_CLK is only available on LPC4370. @@ -112,76 +97,60 @@ put > +/ { > + clocks { > + xtal: xtal { -> + compatible =3D "fixed-clock"; -> + #clock-cells =3D <0>; -> + clock-frequency =3D <12000000>; +> + compatible = "fixed-clock"; +> + #clock-cells = <0>; +> + clock-frequency = <12000000>; > + }; > + > + xtal32: xtal32 { -> + compatible =3D "fixed-clock"; -> + #clock-cells =3D <0>; -> + clock-frequency =3D <32768>; +> + compatible = "fixed-clock"; +> + #clock-cells = <0>; +> + clock-frequency = <32768>; > + }; > + > + enet_rx_clk: enet_rx_clk { -> + compatible =3D "fixed-clock"; -> + #clock-cells =3D <0>; -> + clock-frequency =3D <0>; -> + clock-output-names =3D "enet_rx_clk"; +> + compatible = "fixed-clock"; +> + #clock-cells = <0>; +> + clock-frequency = <0>; +> + clock-output-names = "enet_rx_clk"; > + }; > + > + enet_tx_clk: enet_tx_clk { -> + compatible =3D "fixed-clock"; -> + #clock-cells =3D <0>; -> + clock-frequency =3D <0>; -> + clock-output-names =3D "enet_tx_clk"; +> + compatible = "fixed-clock"; +> + #clock-cells = <0>; +> + clock-frequency = <0>; +> + clock-output-names = "enet_tx_clk"; > + }; > + > + gp_clkin: gp_clkin { -> + compatible =3D "fixed-clock"; -> + #clock-cells =3D <0>; -> + clock-frequency =3D <0>; -> + clock-output-names =3D "gp_clkin"; +> + compatible = "fixed-clock"; +> + #clock-cells = <0>; +> + clock-frequency = <0>; +> + clock-output-names = "gp_clkin"; > + }; > + }; > + > + soc { > + cgu: cgu@40050000 { -> + compatible =3D "nxp,lpc1850-cgu"; -> + reg =3D <0x40050000 0x1000>; -> + #clock-cells =3D <1>; -> + clocks =3D <&xtal>, <&creg_clk 1>, <&enet_rx_clk>= -, <&enet_tx_clk>, <&gp_clkin>; -> + clock-indices =3D <0>, <1>, <2>, <3>, <4>, = -<5>, <6>, <7>, -> + <8>, <9>, <10>, <11>, <12>, <13= ->, <14>, <15>, -> + <16>, <17>, <18>, <19>, <20>, <25= ->, <26>, <27>; -> + clock-output-names =3D "base_safe_clk", "base_= -usb0_clk", -> + "base_periph_clk", "base_us= -b1_clk", -> + "base_cpu_clk", "base_sp= -ifi_clk", -> + "base_spi_clk", "base_ph= -y_rx_clk", -> + "base_phy_tx_clk", "base_ap= -b1_clk", -> + "base_apb3_clk", "base_lc= -d_clk", -> + "base_adchs_clk", "base_sd= -io_clk", -> + "base_ssp0_clk", "base_ss= -p1_clk", -> + "base_uart0_clk", "base_ua= -rt1_clk", -> + "base_uart2_clk", "base_ua= -rt3_clk", -> + "base_out_clk", "base_au= -dio_clk", -> + "base_cgu_out0_clk","base_cg= -u_out1_clk"; +> + compatible = "nxp,lpc1850-cgu"; +> + reg = <0x40050000 0x1000>; +> + #clock-cells = <1>; +> + clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; +> + clock-indices = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, +> + <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, +> + <16>, <17>, <18>, <19>, <20>, <25>, <26>, <27>; +> + clock-output-names = "base_safe_clk", "base_usb0_clk", +> + "base_periph_clk", "base_usb1_clk", +> + "base_cpu_clk", "base_spifi_clk", +> + "base_spi_clk", "base_phy_rx_clk", +> + "base_phy_tx_clk", "base_apb1_clk", +> + "base_apb3_clk", "base_lcd_clk", +> + "base_adchs_clk", "base_sdio_clk", +> + "base_ssp0_clk", "base_ssp1_clk", +> + "base_uart0_clk", "base_uart1_clk", +> + "base_uart2_clk", "base_uart3_clk", +> + "base_out_clk", "base_audio_clk", +> + "base_cgu_out0_clk","base_cgu_out1_clk"; Why do you need to use clock-indices? @@ -199,7 +168,10 @@ Mike > + }; > + }; > +}; -> -- = - +> -- > 1.8.0 ->=20 +> +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N2/content_digest index 5ed4b61..2e3a3e1 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,34 +1,29 @@ "ref\01430170693-28303-1-git-send-email-manabian@gmail.com\0" "ref\01430170693-28303-3-git-send-email-manabian@gmail.com\0" - "From\0Michael Turquette <mturquette@linaro.org>\0" + "ref\01430170693-28303-3-git-send-email-manabian-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" + "From\0Michael Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" "Subject\0Re: [PATCH v2 2/4] doc: dt: add documentation for lpc1850-cgu clk driver\0" "Date\0Tue, 12 May 2015 15:12:02 -0700\0" - "To\0Joachim Eastwood <manabian@gmail.com>" - sboyd@codeaurora.org - arnd@arndb.de - linux-clk@vger.kernel.org - " linux-arm-kernel@lists.infradead.org\0" - "Cc\0devicetree@vger.kernel.org" - ariel.dalessandro@gmail.com - ezequiel@vanguardiasur.com.ar - " Joachim Eastwood <manabian@gmail.com>\0" + "To\0sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org" + arnd-r2nGTMty4D4@public.gmane.org + linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" + "Cc\0devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" + ariel.dalessandro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org + ezequiel-30ULvvUtt6G51wMPkGsGjgyUoB5FGQPZ@public.gmane.org + " Joachim Eastwood <manabian-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" "\00:1\0" "b\0" "Quoting Joachim Eastwood (2015-04-27 14:38:11)\n" "> Add DT binding documentation for lpc1850-cgu driver.\n" - "> =\n" - "\n" - "> Signed-off-by: Joachim Eastwood <manabian@gmail.com>\n" + "> \n" + "> Signed-off-by: Joachim Eastwood <manabian-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" "> ---\n" - "> .../devicetree/bindings/clock/lpc1850-cgu.txt | 138 +++++++++++++++=\n" - "++++++\n" + "> .../devicetree/bindings/clock/lpc1850-cgu.txt | 138 +++++++++++++++++++++\n" "> 1 file changed, 138 insertions(+)\n" - "> create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-cgu.t=\n" - "xt\n" - "> =\n" - "\n" - "> diff --git a/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt b/Do=\n" - "cumentation/devicetree/bindings/clock/lpc1850-cgu.txt\n" + "> create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-cgu.txt\n" + "> \n" + "> diff --git a/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt b/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt\n" "> new file mode 100644\n" "> index 000000000000..0b278ca6aee7\n" "> --- /dev/null\n" @@ -81,27 +76,19 @@ "\n" "> +\n" "> +Number: Name: Description:\n" - "> + 0 BASE_SAFE_CLK Base safe clock (always on) for W=\n" - "WDT\n" + "> + 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT\n" "> + 1 BASE_USB0_CLK Base clock for USB0\n" - "> + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsy=\n" - "stem,\n" + "> + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem,\n" "> + SPI, and SGPIO\n" "> + 3 BASE_USB1_CLK Base clock for USB1\n" - "> + 4 BASE_CPU_CLK System base clock for ARM Cortex-=\n" - "M core\n" - "> + and APB peripheral blocks #0 and =\n" - "#2\n" + "> + 4 BASE_CPU_CLK System base clock for ARM Cortex-M core\n" + "> + and APB peripheral blocks #0 and #2\n" "> + 5 BASE_SPIFI_CLK Base clock for SPIFI\n" "> + 6 BASE_SPI_CLK Base clock for SPI\n" - "> + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Recei=\n" - "ve clock\n" - "> + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Trans=\n" - "mit clock\n" - "> + 9 BASE_APB1_CLK Base clock for APB peripheral blo=\n" - "ck # 1\n" - "> +10 BASE_APB3_CLK Base clock for APB peripheral blo=\n" - "ck # 3\n" + "> + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock\n" + "> + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock\n" + "> + 9 BASE_APB1_CLK Base clock for APB peripheral block # 1\n" + "> +10 BASE_APB3_CLK Base clock for APB peripheral block # 3\n" "> +11 BASE_LCD_CLK Base clock for LCD\n" "> +12 BASE_ADCHS_CLK Base clock for ADCHS\n" "> +13 BASE_SDIO_CLK Base clock for SD/MMC\n" @@ -114,10 +101,8 @@ "> +20 BASE_OUT_CLK Base clock for CLKOUT pin\n" "> +24-21 - Reserved\n" "> +25 BASE_AUDIO_CLK Base clock for audio system (I2S)\n" - "> +26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock out=\n" - "put\n" - "> +27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock out=\n" - "put\n" + "> +26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output\n" + "> +27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output\n" "> +\n" "> +BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx.\n" "> +BASE_ADCHS_CLK is only available on LPC4370.\n" @@ -128,76 +113,60 @@ "> +/ {\n" "> + clocks {\n" "> + xtal: xtal {\n" - "> + compatible =3D \"fixed-clock\";\n" - "> + #clock-cells =3D <0>;\n" - "> + clock-frequency =3D <12000000>;\n" + "> + compatible = \"fixed-clock\";\n" + "> + #clock-cells = <0>;\n" + "> + clock-frequency = <12000000>;\n" "> + };\n" "> +\n" "> + xtal32: xtal32 {\n" - "> + compatible =3D \"fixed-clock\";\n" - "> + #clock-cells =3D <0>;\n" - "> + clock-frequency =3D <32768>;\n" + "> + compatible = \"fixed-clock\";\n" + "> + #clock-cells = <0>;\n" + "> + clock-frequency = <32768>;\n" "> + };\n" "> +\n" "> + enet_rx_clk: enet_rx_clk {\n" - "> + compatible =3D \"fixed-clock\";\n" - "> + #clock-cells =3D <0>;\n" - "> + clock-frequency =3D <0>;\n" - "> + clock-output-names =3D \"enet_rx_clk\";\n" + "> + compatible = \"fixed-clock\";\n" + "> + #clock-cells = <0>;\n" + "> + clock-frequency = <0>;\n" + "> + clock-output-names = \"enet_rx_clk\";\n" "> + };\n" "> +\n" "> + enet_tx_clk: enet_tx_clk {\n" - "> + compatible =3D \"fixed-clock\";\n" - "> + #clock-cells =3D <0>;\n" - "> + clock-frequency =3D <0>;\n" - "> + clock-output-names =3D \"enet_tx_clk\";\n" + "> + compatible = \"fixed-clock\";\n" + "> + #clock-cells = <0>;\n" + "> + clock-frequency = <0>;\n" + "> + clock-output-names = \"enet_tx_clk\";\n" "> + };\n" "> +\n" "> + gp_clkin: gp_clkin {\n" - "> + compatible =3D \"fixed-clock\";\n" - "> + #clock-cells =3D <0>;\n" - "> + clock-frequency =3D <0>;\n" - "> + clock-output-names =3D \"gp_clkin\";\n" + "> + compatible = \"fixed-clock\";\n" + "> + #clock-cells = <0>;\n" + "> + clock-frequency = <0>;\n" + "> + clock-output-names = \"gp_clkin\";\n" "> + };\n" "> + };\n" "> +\n" "> + soc {\n" "> + cgu: cgu@40050000 {\n" - "> + compatible =3D \"nxp,lpc1850-cgu\";\n" - "> + reg =3D <0x40050000 0x1000>;\n" - "> + #clock-cells =3D <1>;\n" - "> + clocks =3D <&xtal>, <&creg_clk 1>, <&enet_rx_clk>=\n" - ", <&enet_tx_clk>, <&gp_clkin>;\n" - "> + clock-indices =3D <0>, <1>, <2>, <3>, <4>, =\n" - "<5>, <6>, <7>,\n" - "> + <8>, <9>, <10>, <11>, <12>, <13=\n" - ">, <14>, <15>,\n" - "> + <16>, <17>, <18>, <19>, <20>, <25=\n" - ">, <26>, <27>;\n" - "> + clock-output-names =3D \"base_safe_clk\", \"base_=\n" - "usb0_clk\",\n" - "> + \"base_periph_clk\", \"base_us=\n" - "b1_clk\",\n" - "> + \"base_cpu_clk\", \"base_sp=\n" - "ifi_clk\",\n" - "> + \"base_spi_clk\", \"base_ph=\n" - "y_rx_clk\",\n" - "> + \"base_phy_tx_clk\", \"base_ap=\n" - "b1_clk\",\n" - "> + \"base_apb3_clk\", \"base_lc=\n" - "d_clk\",\n" - "> + \"base_adchs_clk\", \"base_sd=\n" - "io_clk\",\n" - "> + \"base_ssp0_clk\", \"base_ss=\n" - "p1_clk\",\n" - "> + \"base_uart0_clk\", \"base_ua=\n" - "rt1_clk\",\n" - "> + \"base_uart2_clk\", \"base_ua=\n" - "rt3_clk\",\n" - "> + \"base_out_clk\", \"base_au=\n" - "dio_clk\",\n" - "> + \"base_cgu_out0_clk\",\"base_cg=\n" - "u_out1_clk\";\n" + "> + compatible = \"nxp,lpc1850-cgu\";\n" + "> + reg = <0x40050000 0x1000>;\n" + "> + #clock-cells = <1>;\n" + "> + clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;\n" + "> + clock-indices = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,\n" + "> + <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>,\n" + "> + <16>, <17>, <18>, <19>, <20>, <25>, <26>, <27>;\n" + "> + clock-output-names = \"base_safe_clk\", \"base_usb0_clk\",\n" + "> + \"base_periph_clk\", \"base_usb1_clk\",\n" + "> + \"base_cpu_clk\", \"base_spifi_clk\",\n" + "> + \"base_spi_clk\", \"base_phy_rx_clk\",\n" + "> + \"base_phy_tx_clk\", \"base_apb1_clk\",\n" + "> + \"base_apb3_clk\", \"base_lcd_clk\",\n" + "> + \"base_adchs_clk\", \"base_sdio_clk\",\n" + "> + \"base_ssp0_clk\", \"base_ssp1_clk\",\n" + "> + \"base_uart0_clk\", \"base_uart1_clk\",\n" + "> + \"base_uart2_clk\", \"base_uart3_clk\",\n" + "> + \"base_out_clk\", \"base_audio_clk\",\n" + "> + \"base_cgu_out0_clk\",\"base_cgu_out1_clk\";\n" "\n" "Why do you need to use clock-indices?\n" "\n" @@ -215,9 +184,12 @@ "> + };\n" "> + };\n" "> +};\n" - "> -- =\n" - "\n" + "> -- \n" "> 1.8.0\n" - >=20 + "> \n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -e56187fbba3cae487073dcea2674a8bf1a0b81a9a4197fb3ece60acebcac9cfb +e6788bd7b4396954864b3d26176fedbd79f1f13f1ad4b9197b1f2e8bb48d6cca
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.