diff for duplicates of <20150512232549.16410.5974@quantum> diff --git a/a/1.txt b/N1/1.txt index 0d249af..466f359 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -3,42 +3,33 @@ Quoting Joonyoung Shim (2015-04-07 00:46:46) > of divider with CLK_DIVIDER_READ_ONLY flag. If be used > CLK_SET_RATE_PARENT flag with CLK_DIVIDER_READ_ONLY flag, then never > change parent clk rate anymore. -> = - +> > From this case, this patch allows to change parent clk rate. -> = - +> > Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> > --- > drivers/clk/clk-divider.c | 5 +++++ > 1 file changed, 5 insertions(+) -> = - +> > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c > index ce34d29a..37e285e 100644 > --- a/drivers/clk/clk-divider.c > +++ b/drivers/clk/clk-divider.c -> @@ -352,6 +352,11 @@ static long clk_divider_round_rate(struct clk_hw *hw= -, unsigned long rate, -> bestdiv =3D readl(divider->reg) >> divider->shift; -> bestdiv &=3D div_mask(divider->width); -> bestdiv =3D _get_div(divider->table, bestdiv, divider->fl= -ags); +> @@ -352,6 +352,11 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, +> bestdiv = readl(divider->reg) >> divider->shift; +> bestdiv &= div_mask(divider->width); +> bestdiv = _get_div(divider->table, bestdiv, divider->flags); > + > + if ((__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) -> + *prate =3D __clk_round_rate(__clk_get_parent(hw->= -clk), +> + *prate = __clk_round_rate(__clk_get_parent(hw->clk), > + rate); > + > return DIV_ROUND_UP(*prate, bestdiv); > } -> = - -> -- = - +> +> -- > 1.9.1 -> = - +> Hello Joonyoung Shim, @@ -53,7 +44,7 @@ Mike -From=20655dddad2700a30aaa397cd804422e0d9195efad Mon Sep 17 00:00:00 2001 +>From 655dddad2700a30aaa397cd804422e0d9195efad Mon Sep 17 00:00:00 2001 From: Michael Turquette <mturquette@linaro.org> Date: Tue, 12 May 2015 16:13:46 -0700 Subject: [PATCH] clk: divider: support read-only dividers @@ -80,33 +71,29 @@ diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 25006a8..5d2de26 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c -@@ -412,6 +412,11 @@ const struct clk_ops clk_divider_ops =3D { +@@ -412,6 +412,11 @@ const struct clk_ops clk_divider_ops = { }; EXPORT_SYMBOL_GPL(clk_divider_ops); - = - -+const struct clk_ops clk_divider_ro_ops =3D { -+ .recalc_rate =3D clk_divider_recalc_rate, + ++const struct clk_ops clk_divider_ro_ops = { ++ .recalc_rate = clk_divider_recalc_rate, +}; +EXPORT_SYMBOL_GPL(clk_divider_ro_ops); + static struct clk *_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, -@@ -437,7 +442,10 @@ static struct clk *_register_divider(struct device *de= -v, const char *name, +@@ -437,7 +442,10 @@ static struct clk *_register_divider(struct device *dev, const char *name, } - = - - init.name =3D name; -- init.ops =3D &clk_divider_ops; + + init.name = name; +- init.ops = &clk_divider_ops; + if (clk_divider_flags & CLK_DIVIDER_READ_ONLY) -+ init.ops =3D &clk_divider_ro_ops; ++ init.ops = &clk_divider_ro_ops; + else -+ init.ops =3D &clk_divider_ops; - init.flags =3D flags | CLK_IS_BASIC; - init.parent_names =3D (parent_name ? &parent_name: NULL); - init.num_parents =3D (parent_name ? 1 : 0); --- = - ++ init.ops = &clk_divider_ops; + init.flags = flags | CLK_IS_BASIC; + init.parent_names = (parent_name ? &parent_name: NULL); + init.num_parents = (parent_name ? 1 : 0); +-- 1.9.1 diff --git a/a/content_digest b/N1/content_digest index 9338660..63d02e6 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -17,42 +17,33 @@ "> of divider with CLK_DIVIDER_READ_ONLY flag. If be used\n" "> CLK_SET_RATE_PARENT flag with CLK_DIVIDER_READ_ONLY flag, then never\n" "> change parent clk rate anymore.\n" - "> =\n" - "\n" + "> \n" "> From this case, this patch allows to change parent clk rate.\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>\n" "> ---\n" "> drivers/clk/clk-divider.c | 5 +++++\n" "> 1 file changed, 5 insertions(+)\n" - "> =\n" - "\n" + "> \n" "> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c\n" "> index ce34d29a..37e285e 100644\n" "> --- a/drivers/clk/clk-divider.c\n" "> +++ b/drivers/clk/clk-divider.c\n" - "> @@ -352,6 +352,11 @@ static long clk_divider_round_rate(struct clk_hw *hw=\n" - ", unsigned long rate,\n" - "> bestdiv =3D readl(divider->reg) >> divider->shift;\n" - "> bestdiv &=3D div_mask(divider->width);\n" - "> bestdiv =3D _get_div(divider->table, bestdiv, divider->fl=\n" - "ags);\n" + "> @@ -352,6 +352,11 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,\n" + "> bestdiv = readl(divider->reg) >> divider->shift;\n" + "> bestdiv &= div_mask(divider->width);\n" + "> bestdiv = _get_div(divider->table, bestdiv, divider->flags);\n" "> +\n" "> + if ((__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT))\n" - "> + *prate =3D __clk_round_rate(__clk_get_parent(hw->=\n" - "clk),\n" + "> + *prate = __clk_round_rate(__clk_get_parent(hw->clk),\n" "> + rate);\n" "> +\n" "> return DIV_ROUND_UP(*prate, bestdiv);\n" "> }\n" - "> =\n" - "\n" - "> -- =\n" - "\n" + "> \n" + "> -- \n" "> 1.9.1\n" - "> =\n" - "\n" + "> \n" "\n" "Hello Joonyoung Shim,\n" "\n" @@ -67,7 +58,7 @@ "\n" "\n" "\n" - "From=20655dddad2700a30aaa397cd804422e0d9195efad Mon Sep 17 00:00:00 2001\n" + ">From 655dddad2700a30aaa397cd804422e0d9195efad Mon Sep 17 00:00:00 2001\n" "From: Michael Turquette <mturquette@linaro.org>\n" "Date: Tue, 12 May 2015 16:13:46 -0700\n" "Subject: [PATCH] clk: divider: support read-only dividers\n" @@ -94,35 +85,31 @@ "index 25006a8..5d2de26 100644\n" "--- a/drivers/clk/clk-divider.c\n" "+++ b/drivers/clk/clk-divider.c\n" - "@@ -412,6 +412,11 @@ const struct clk_ops clk_divider_ops =3D {\n" + "@@ -412,6 +412,11 @@ const struct clk_ops clk_divider_ops = {\n" " };\n" " EXPORT_SYMBOL_GPL(clk_divider_ops);\n" - " =\n" - "\n" - "+const struct clk_ops clk_divider_ro_ops =3D {\n" - "+\t.recalc_rate =3D clk_divider_recalc_rate,\n" + " \n" + "+const struct clk_ops clk_divider_ro_ops = {\n" + "+\t.recalc_rate = clk_divider_recalc_rate,\n" "+};\n" "+EXPORT_SYMBOL_GPL(clk_divider_ro_ops);\n" "+\n" " static struct clk *_register_divider(struct device *dev, const char *name,\n" " \t\tconst char *parent_name, unsigned long flags,\n" " \t\tvoid __iomem *reg, u8 shift, u8 width,\n" - "@@ -437,7 +442,10 @@ static struct clk *_register_divider(struct device *de=\n" - "v, const char *name,\n" + "@@ -437,7 +442,10 @@ static struct clk *_register_divider(struct device *dev, const char *name,\n" " \t}\n" - " =\n" - "\n" - " \tinit.name =3D name;\n" - "-\tinit.ops =3D &clk_divider_ops;\n" + " \n" + " \tinit.name = name;\n" + "-\tinit.ops = &clk_divider_ops;\n" "+\tif (clk_divider_flags & CLK_DIVIDER_READ_ONLY)\n" - "+\t\tinit.ops =3D &clk_divider_ro_ops;\n" + "+\t\tinit.ops = &clk_divider_ro_ops;\n" "+\telse\n" - "+\t\tinit.ops =3D &clk_divider_ops;\n" - " \tinit.flags =3D flags | CLK_IS_BASIC;\n" - " \tinit.parent_names =3D (parent_name ? &parent_name: NULL);\n" - " \tinit.num_parents =3D (parent_name ? 1 : 0);\n" - "-- =\n" - "\n" + "+\t\tinit.ops = &clk_divider_ops;\n" + " \tinit.flags = flags | CLK_IS_BASIC;\n" + " \tinit.parent_names = (parent_name ? &parent_name: NULL);\n" + " \tinit.num_parents = (parent_name ? 1 : 0);\n" + "-- \n" 1.9.1 -884a2f0ecc45786f217a0323e4fa98949af3561382a9c6c290049b8181a8965c +14122eaba4dcffdf3c9ac4e8c3600f6055ec91b2ca8e0abcd2e0e337390002bb
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