Re: [Qemu-devel] [PATCH target-arm v8 00/14] Next Generation Xilinx Zynq SoC

["Edgar E. Iglesias" <edgar.iglesias@xilinx.com>]

On Mon, May 11, 2015 at 03:45:47PM -0700, Peter Crosthwaite wrote:
> Hi Peter and all,
> 
> Xilinx's next gen SoC has been announced. This series adds a SoC and
> board.


Hi Peter,

Did you by accident send out v8 twice instead of a v9?

Cheers,
Edgar



> 
> Series start with addition of ARM cortex A53 support (P1 and P2). The
> Soc skeleton is then added with GIC, EMACs and UARTs added. The
> pre-existing models for GEM and UART are not SoC friendly (no visible
> state struct), so those are refactored for SoC.
> 
> Create a model of the EP108 board. Currently this doesn't have any
> EP108 specific features but is a usable board exposing the user visible
> features of the raw SoC.
> 
> See individual patches for detailed change logs.
> 
> changed since v7 (PMM review):
> made GIC region sz defs board specific.
> 
> changed since v6 (Edgar review):
> Added GIC region size macro
> Added GIC alises
> 
> changed since v4:
> Addressed PMM and Alistair Reviews
> 
> changed since v3:
> Included CPU thread kick fix
> Addressed Alistair review
> 
> changed since v2:
> Fix CPU child prop adder
> Add DTS compat string
> 
> changed since v1:
> Addressed Alistair review (individual changes on resp. patches)
> Changed board name to EP108
> Changed naming scheme to "zynqmp" / "ZYNQMP" (Michal review)
> 
> Regards,
> Peter
> 
> 
> Peter Crosthwaite (14):
>   target-arm: cpu64: generalise name of A57 regs
>   target-arm: cpu64: Add support for Cortex-A53
>   arm: Introduce Xilinx ZynqMP SoC
>   arm: xlnx-zynqmp: Add GIC
>   arm: xlnx-zynqmp: Connect CPU Timers to GIC
>   net: cadence_gem: Clean up variable names
>   net: cadence_gem: Split state struct and type into header
>   arm: xlnx-zynqmp: Add GEM support
>   char: cadence_uart: Clean up variable names
>   char: cadence_uart: Split state struct and type into header
>   arm: xlnx-zynqmp: Add UART support
>   arm: Add xlnx-ep108 machine
>   arm: xlnx-ep108: Add external RAM
>   arm: xlnx-ep108: Add bootloading
> 
>  default-configs/aarch64-softmmu.mak |   2 +-
>  hw/arm/Makefile.objs                |   1 +
>  hw/arm/xlnx-ep108.c                 |  82 ++++++++++++++
>  hw/arm/xlnx-zynqmp.c                | 211 ++++++++++++++++++++++++++++++++++++
>  hw/char/cadence_uart.c              | 115 ++++++++------------
>  hw/net/cadence_gem.c                |  95 +++++-----------
>  include/hw/arm/xlnx-zynqmp.h        |  58 ++++++++++
>  include/hw/char/cadence_uart.h      |  53 +++++++++
>  include/hw/net/cadence_gem.h        |  73 +++++++++++++
>  target-arm/cpu64.c                  |  61 ++++++++++-
>  10 files changed, 609 insertions(+), 142 deletions(-)
>  create mode 100644 hw/arm/xlnx-ep108.c
>  create mode 100644 hw/arm/xlnx-zynqmp.c
>  create mode 100644 include/hw/arm/xlnx-zynqmp.h
>  create mode 100644 include/hw/char/cadence_uart.h
>  create mode 100644 include/hw/net/cadence_gem.h
> 
> -- 
> 2.4.0.3.ge0ccc3b.dirty
>