From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Edgar Iglesias" <edgar.iglesias@xilinx.com>,
"Alexander Graf" <agraf@suse.de>,
"QEMU Developers" <qemu-devel@nongnu.org>,
"Greg Bellows" <greg.bellows@linaro.org>,
"Sergey Fedorov" <serge.fdrv@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>
Subject: Re: [Qemu-devel] [PATCH v1 04/18] target-arm: Route timer access traps to EL1
Date: Tue, 19 May 2015 09:27:24 +1000 [thread overview]
Message-ID: <20150518232724.GA10142@toto> (raw)
In-Reply-To: <CAFEAcA8ZrkJVtG3vLrb0DtjrhLig3J=1WSAtW6YsdQJjkwNa3g@mail.gmail.com>
On Mon, May 18, 2015 at 07:41:29PM +0100, Peter Maydell wrote:
> On 13 May 2015 at 07:52, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> > target-arm/helper.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/target-arm/helper.c b/target-arm/helper.c
> > index a4bab78..d849b30 100644
> > --- a/target-arm/helper.c
> > +++ b/target-arm/helper.c
> > @@ -1147,6 +1147,7 @@ static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
> > {
> > /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
> > if (arm_current_el(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
> > + env->exception.target_el = 1;
> > return CP_ACCESS_TRAP;
> > }
> > return CP_ACCESS_OK;
> > @@ -1157,6 +1158,7 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
> > /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
> > if (arm_current_el(env) == 0 &&
> > !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
> > + env->exception.target_el = 1;
> > return CP_ACCESS_TRAP;
> > }
> > return CP_ACCESS_OK;
> > @@ -1169,6 +1171,7 @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
> > */
> > if (arm_current_el(env) == 0 &&
> > !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
> > + env->exception.target_el = 1;
> > return CP_ACCESS_TRAP;
> > }
> > return CP_ACCESS_OK;
>
> If EL3 is 32-bit and we're in Secure EL0 then the correct
> target_el is 3, not 1, so what you actually want here is
> exception_target_el().
>
> More generally, this seems to be a really easy mistake to make
> with access functions. At the moment we come pretty close to
> being able to say "always set both exception.target_el and
> exception.syndrome in the same place in the code". So I think
> the correct fix is
>
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -333,9 +333,11 @@ void HELPER(access_check_cp_reg)(CPUARMState
> *env, void *rip, uint32_t syndrome)
> return;
> case CP_ACCESS_TRAP:
> env->exception.syndrome = syndrome;
> + env->target_el = exception_target_el(env);
> break;
> case CP_ACCESS_TRAP_UNCATEGORIZED:
> env->exception.syndrome = syn_uncategorized();
> + env->target_el = exception_target_el(env);
> break;
> default:
> g_assert_not_reached();
>
> in the "Extend helpers to route exceptions" patch. If we
> get any registers where the correct target EL is something
> other than that, we should have new CP_ACCESS_* enums for
> them.
>
> Then the only place where we don't set both syndrome
> and target_el at the same time are:
> * msr_i_pstate is failing to set a syndrome
> * arm_debug_excp_handler() needs to set the target_el
> to the debug target el
> * arm_cpu_handle_mmu_fault should set the target_el
> * the FIQ/IRQ/VIRQ/VFIQ paths in arm_cpu_exec_interrupt
> don't set syndrome, because they're interrupts and
> there's no syndrome info
>
> Note that the first three of these are all bugs, which is
> a nice demonstration of the utility of the rule. I think
> I'd also like to make the FIQ&c code set exception.syndrome
> to an invalid value, because then we can probably write
> some assertions for exception entry (and also because then
> we're consistent about things.)
>
> That seems like more than I really feel I can justify
> just fixing in target-arm.next, so I think I'll drop
> Greg's patches 1..3 from target-arm.next and send them
> out as part of a series which does the above changes.
>
Sounds good, thanks!
Cheers,
Edgar
next prev parent reply other threads:[~2015-05-18 23:31 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-13 6:52 [Qemu-devel] [PATCH v1 00/18] arm: Steps towards EL2 support round 3 Edgar E. Iglesias
2015-05-13 6:52 ` [Qemu-devel] [PATCH v1 01/18] target-arm: Correct accessfn for CNTP_{CT}VAL_EL0 Edgar E. Iglesias
2015-05-13 6:52 ` [Qemu-devel] [PATCH v1 02/18] target-arm: Correct accessfn for CNTV_TVAL_EL0 Edgar E. Iglesias
2015-05-13 6:52 ` [Qemu-devel] [PATCH v1 03/18] target-arm: Remove unneeded '+' Edgar E. Iglesias
2015-05-14 9:11 ` Alex Bennée
2015-05-13 6:52 ` [Qemu-devel] [PATCH v1 04/18] target-arm: Route timer access traps to EL1 Edgar E. Iglesias
2015-05-18 18:41 ` Peter Maydell
2015-05-18 23:27 ` Edgar E. Iglesias [this message]
2015-05-13 6:52 ` [Qemu-devel] [PATCH v1 05/18] target-arm: Add MAIR_EL2 Edgar E. Iglesias
2015-05-13 7:52 ` Sergey Fedorov
2015-05-13 11:05 ` Edgar E. Iglesias
2015-05-13 11:09 ` Sergey Fedorov
2015-05-18 18:49 ` Peter Maydell
2015-05-13 6:52 ` [Qemu-devel] [PATCH v1 06/18] target-arm: Add TCR_EL2 Edgar E. Iglesias
2015-05-18 18:51 ` Peter Maydell
2015-05-13 6:52 ` [Qemu-devel] [PATCH v1 07/18] target-arm: Add SCTLR_EL2 Edgar E. Iglesias
2015-05-13 6:52 ` [Qemu-devel] [PATCH v1 08/18] target-arm: Add TTBR0_EL2 Edgar E. Iglesias
2015-05-13 6:52 ` [Qemu-devel] [PATCH v1 09/18] target-arm: Add TLBI_ALLE1{IS} Edgar E. Iglesias
2015-05-13 6:52 ` [Qemu-devel] [PATCH v1 10/18] target-arm: Add TLBIALLE2 Edgar E. Iglesias
2015-05-13 6:52 ` [Qemu-devel] [PATCH v1 11/18] target-arm: Add TPIDR_EL2 Edgar E. Iglesias
2015-05-13 6:52 ` [Qemu-devel] [PATCH v1 12/18] target-arm: Add TLBI_VAE2{IS} Edgar E. Iglesias
2015-05-13 6:52 ` [Qemu-devel] [PATCH v1 13/18] target-arm: Add access to PAR_EL1 Edgar E. Iglesias
2015-05-13 6:52 ` [Qemu-devel] [PATCH v1 14/18] target-arm: Add CNTVOFF_EL2 Edgar E. Iglesias
2015-05-13 6:52 ` [Qemu-devel] [PATCH v1 15/18] target-arm: Add CNTHCTL_EL2 Edgar E. Iglesias
2015-05-13 6:52 ` [Qemu-devel] [PATCH v1 16/18] target-arm: Pass timeridx as argument to various timer functions Edgar E. Iglesias
2015-05-13 6:52 ` [Qemu-devel] [PATCH v1 17/18] target-arm: Add HYP timer Edgar E. Iglesias
2015-05-13 6:52 ` [Qemu-devel] [PATCH v1 18/18] hw/arm/virt: Connect the Hypervisor timer Edgar E. Iglesias
2015-05-18 18:53 ` [Qemu-devel] [PATCH v1 00/18] arm: Steps towards EL2 support round 3 Peter Maydell
2015-05-18 23:38 ` Edgar E. Iglesias
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20150518232724.GA10142@toto \
--to=edgar.iglesias@gmail.com \
--cc=agraf@suse.de \
--cc=alex.bennee@linaro.org \
--cc=edgar.iglesias@xilinx.com \
--cc=greg.bellows@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=serge.fdrv@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.