diff for duplicates of <20150520033956.9817.55602@quantum> diff --git a/a/1.txt b/N1/1.txt index b7ca20d..f5a36e0 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,12 +1,10 @@ Quoting Thierry Reding (2015-05-07 08:23:39) > From: Thierry Reding <treding@nvidia.com> -> = - +> > Benson Leung pointed out that the kerneldoc for this structure has > become stale. Update the field descriptions to match the structure > content. -> = - +> > Reported-by: Benson Leung <bleung@chromium.org> > Acked-by: Rhyland Klein <rklein@nvidia.com> > Signed-off-by: Thierry Reding <treding@nvidia.com> @@ -19,20 +17,17 @@ Mike > --- > Changes in v2: > - document max_p and pdiv_tohw fields -> = - +> > drivers/clk/tegra/clk.h | 18 +++++++++++++++--- > 1 file changed, 15 insertions(+), 3 deletions(-) -> = - +> > diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h > index f3782dedbdfb..b76b786e15f6 100644 > --- a/drivers/clk/tegra/clk.h > +++ b/drivers/clk/tegra/clk.h > @@ -157,7 +157,7 @@ struct div_nmp { > }; -> = - +> > /** > - * struct clk_pll_params - PLL parameters > + * struct tegra_clk_pll_params - PLL parameters @@ -51,26 +46,21 @@ Mike > + * @aux_reg: AUX register offset > + * @dyn_ramp_reg: Dynamic ramp control register offset > + * @ext_misc_reg: Miscellaneous control register offsets -> + * @pmc_divnm_reg: n, m divider PMC override register offset= - (PLLM) -> + * @pmc_divp_reg: p divider PMC override register offset (P= -LLM) +> + * @pmc_divnm_reg: n, m divider PMC override register offset (PLLM) +> + * @pmc_divp_reg: p divider PMC override register offset (PLLM) > + * @flags: PLL flags > + * @stepa_shift: Dynamic ramp step A field shift > + * @stepb_shift: Dynamic ramp step B field shift -> * @lock_delay: Delay in us if PLL lock is not us= -ed +> * @lock_delay: Delay in us if PLL lock is not used > + * @max_p: maximum value for the p divider > + * @pdiv_tohw: mapping of p divider to register values > + * @div_nmp: offsets and widths on n, m and p fields -> * @freq_table: array of frequencies supported by= - PLL +> * @freq_table: array of frequencies supported by PLL > * @fixed_rate: PLL rate if it is fixed > - * @flags: PLL flags > * > * Flags: > * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for -> -- = - +> -- > 2.3.5 ->=20 +> diff --git a/a/content_digest b/N1/content_digest index eac18fe..eec4e3c 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -17,13 +17,11 @@ "b\0" "Quoting Thierry Reding (2015-05-07 08:23:39)\n" "> From: Thierry Reding <treding@nvidia.com>\n" - "> =\n" - "\n" + "> \n" "> Benson Leung pointed out that the kerneldoc for this structure has\n" "> become stale. Update the field descriptions to match the structure\n" "> content.\n" - "> =\n" - "\n" + "> \n" "> Reported-by: Benson Leung <bleung@chromium.org>\n" "> Acked-by: Rhyland Klein <rklein@nvidia.com>\n" "> Signed-off-by: Thierry Reding <treding@nvidia.com>\n" @@ -36,20 +34,17 @@ "> ---\n" "> Changes in v2:\n" "> - document max_p and pdiv_tohw fields\n" - "> =\n" - "\n" + "> \n" "> drivers/clk/tegra/clk.h | 18 +++++++++++++++---\n" "> 1 file changed, 15 insertions(+), 3 deletions(-)\n" - "> =\n" - "\n" + "> \n" "> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h\n" "> index f3782dedbdfb..b76b786e15f6 100644\n" "> --- a/drivers/clk/tegra/clk.h\n" "> +++ b/drivers/clk/tegra/clk.h\n" "> @@ -157,7 +157,7 @@ struct div_nmp {\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /**\n" "> - * struct clk_pll_params - PLL parameters\n" "> + * struct tegra_clk_pll_params - PLL parameters\n" @@ -68,28 +63,23 @@ "> + * @aux_reg: AUX register offset\n" "> + * @dyn_ramp_reg: Dynamic ramp control register offset\n" "> + * @ext_misc_reg: Miscellaneous control register offsets\n" - "> + * @pmc_divnm_reg: n, m divider PMC override register offset=\n" - " (PLLM)\n" - "> + * @pmc_divp_reg: p divider PMC override register offset (P=\n" - "LLM)\n" + "> + * @pmc_divnm_reg: n, m divider PMC override register offset (PLLM)\n" + "> + * @pmc_divp_reg: p divider PMC override register offset (PLLM)\n" "> + * @flags: PLL flags\n" "> + * @stepa_shift: Dynamic ramp step A field shift\n" "> + * @stepb_shift: Dynamic ramp step B field shift\n" - "> * @lock_delay: Delay in us if PLL lock is not us=\n" - "ed\n" + "> * @lock_delay: Delay in us if PLL lock is not used\n" "> + * @max_p: maximum value for the p divider\n" "> + * @pdiv_tohw: mapping of p divider to register values\n" "> + * @div_nmp: offsets and widths on n, m and p fields\n" - "> * @freq_table: array of frequencies supported by=\n" - " PLL\n" + "> * @freq_table: array of frequencies supported by PLL\n" "> * @fixed_rate: PLL rate if it is fixed\n" "> - * @flags: PLL flags\n" "> *\n" "> * Flags:\n" "> * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for\n" - "> -- =\n" - "\n" + "> -- \n" "> 2.3.5\n" - >=20 + > -3f65958e0899eb3934cd7539a219aee142fd305efcf1132abcd16d0899096a81 +827b1869657f6a4d7ce670178e5bc2c3b59954c143455115e27964d3325d8096
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