diff for duplicates of <20150521211727.9817.5989@quantum> diff --git a/a/1.txt b/N1/1.txt index d4413ad..54c8aae 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -5,14 +5,11 @@ Quoting Joachim Eastwood (2015-05-13 00:57:18) > >> > >> Signed-off-by: Joachim Eastwood <manabian@gmail.com> > >> --- -> >> .../devicetree/bindings/clock/lpc1850-cgu.txt | 138 ++++++++++++= -+++++++++ +> >> .../devicetree/bindings/clock/lpc1850-cgu.txt | 138 +++++++++++++++++++++ > >> 1 file changed, 138 insertions(+) -> >> create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-cg= -u.txt +> >> create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-cgu.txt > >> -> >> diff --git a/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt b= -/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt +> >> diff --git a/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt b/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt > >> new file mode 100644 > >> index 000000000000..0b278ca6aee7 > >> --- /dev/null @@ -65,27 +62,19 @@ u.txt > > > >> + > >> +Number: Name: Description: -> >> + 0 BASE_SAFE_CLK Base safe clock (always on) fo= -r WWDT +> >> + 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT > >> + 1 BASE_USB0_CLK Base clock for USB0 -> >> + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB su= -bsystem, +> >> + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem, > >> + SPI, and SGPIO > >> + 3 BASE_USB1_CLK Base clock for USB1 -> >> + 4 BASE_CPU_CLK System base clock for ARM Cort= -ex-M core -> >> + and APB peripheral blocks #0 a= -nd #2 +> >> + 4 BASE_CPU_CLK System base clock for ARM Cortex-M core +> >> + and APB peripheral blocks #0 and #2 > >> + 5 BASE_SPIFI_CLK Base clock for SPIFI > >> + 6 BASE_SPI_CLK Base clock for SPI -> >> + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Re= -ceive clock -> >> + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Tr= -ansmit clock -> >> + 9 BASE_APB1_CLK Base clock for APB peripheral = -block # 1 -> >> +10 BASE_APB3_CLK Base clock for APB peripheral = -block # 3 +> >> + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock +> >> + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock +> >> + 9 BASE_APB1_CLK Base clock for APB peripheral block # 1 +> >> +10 BASE_APB3_CLK Base clock for APB peripheral block # 3 > >> +11 BASE_LCD_CLK Base clock for LCD > >> +12 BASE_ADCHS_CLK Base clock for ADCHS > >> +13 BASE_SDIO_CLK Base clock for SD/MMC @@ -97,12 +86,9 @@ block # 3 > >> +19 BASE_UART3_CLK Base clock for UART3 > >> +20 BASE_OUT_CLK Base clock for CLKOUT pin > >> +24-21 - Reserved -> >> +25 BASE_AUDIO_CLK Base clock for audio system (I= -2S) -> >> +26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock = -output -> >> +27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock = -output +> >> +25 BASE_AUDIO_CLK Base clock for audio system (I2S) +> >> +26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output +> >> +27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output > >> + > >> +BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx. > >> +BASE_ADCHS_CLK is only available on LPC4370. @@ -113,96 +99,76 @@ output > >> +/ { > >> + clocks { > >> + xtal: xtal { -> >> + compatible =3D "fixed-clock"; -> >> + #clock-cells =3D <0>; -> >> + clock-frequency =3D <12000000>; +> >> + compatible = "fixed-clock"; +> >> + #clock-cells = <0>; +> >> + clock-frequency = <12000000>; > >> + }; > >> + > >> + xtal32: xtal32 { -> >> + compatible =3D "fixed-clock"; -> >> + #clock-cells =3D <0>; -> >> + clock-frequency =3D <32768>; +> >> + compatible = "fixed-clock"; +> >> + #clock-cells = <0>; +> >> + clock-frequency = <32768>; > >> + }; > >> + > >> + enet_rx_clk: enet_rx_clk { -> >> + compatible =3D "fixed-clock"; -> >> + #clock-cells =3D <0>; -> >> + clock-frequency =3D <0>; -> >> + clock-output-names =3D "enet_rx_clk"; +> >> + compatible = "fixed-clock"; +> >> + #clock-cells = <0>; +> >> + clock-frequency = <0>; +> >> + clock-output-names = "enet_rx_clk"; > >> + }; > >> + > >> + enet_tx_clk: enet_tx_clk { -> >> + compatible =3D "fixed-clock"; -> >> + #clock-cells =3D <0>; -> >> + clock-frequency =3D <0>; -> >> + clock-output-names =3D "enet_tx_clk"; +> >> + compatible = "fixed-clock"; +> >> + #clock-cells = <0>; +> >> + clock-frequency = <0>; +> >> + clock-output-names = "enet_tx_clk"; > >> + }; > >> + > >> + gp_clkin: gp_clkin { -> >> + compatible =3D "fixed-clock"; -> >> + #clock-cells =3D <0>; -> >> + clock-frequency =3D <0>; -> >> + clock-output-names =3D "gp_clkin"; +> >> + compatible = "fixed-clock"; +> >> + #clock-cells = <0>; +> >> + clock-frequency = <0>; +> >> + clock-output-names = "gp_clkin"; > >> + }; > >> + }; > >> + > >> + soc { -> >> + cgu: cgu@40050000 { -> >> + compatible =3D "nxp,lpc1850-cgu"; -> >> + reg =3D <0x40050000 0x1000>; -> >> + #clock-cells =3D <1>; -> >> + clocks =3D <&xtal>, <&creg_clk 1>, <&enet_rx_c= -lk>, <&enet_tx_clk>, <&gp_clkin>; -> >> + clock-indices =3D <0>, <1>, <2>, <3>, <4>= -, <5>, <6>, <7>, -> >> + <8>, <9>, <10>, <11>, <12>, = -<13>, <14>, <15>, -> >> + <16>, <17>, <18>, <19>, <20>, = -<25>, <26>, <27>; -> >> + clock-output-names =3D "base_safe_clk", "ba= -se_usb0_clk", -> >> + "base_periph_clk", "base= -_usb1_clk", -> >> + "base_cpu_clk", "base= -_spifi_clk", -> >> + "base_spi_clk", "base= -_phy_rx_clk", -> >> + "base_phy_tx_clk", "base= -_apb1_clk", -> >> + "base_apb3_clk", "base= -_lcd_clk", -> >> + "base_adchs_clk", "base= -_sdio_clk", -> >> + "base_ssp0_clk", "base= -_ssp1_clk", -> >> + "base_uart0_clk", "base= -_uart1_clk", -> >> + "base_uart2_clk", "base= -_uart3_clk", -> >> + "base_out_clk", "base= -_audio_clk", -> >> + "base_cgu_out0_clk","base= -_cgu_out1_clk"; +> >> + cgu: cgu at 40050000 { +> >> + compatible = "nxp,lpc1850-cgu"; +> >> + reg = <0x40050000 0x1000>; +> >> + #clock-cells = <1>; +> >> + clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; +> >> + clock-indices = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, +> >> + <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, +> >> + <16>, <17>, <18>, <19>, <20>, <25>, <26>, <27>; +> >> + clock-output-names = "base_safe_clk", "base_usb0_clk", +> >> + "base_periph_clk", "base_usb1_clk", +> >> + "base_cpu_clk", "base_spifi_clk", +> >> + "base_spi_clk", "base_phy_rx_clk", +> >> + "base_phy_tx_clk", "base_apb1_clk", +> >> + "base_apb3_clk", "base_lcd_clk", +> >> + "base_adchs_clk", "base_sdio_clk", +> >> + "base_ssp0_clk", "base_ssp1_clk", +> >> + "base_uart0_clk", "base_uart1_clk", +> >> + "base_uart2_clk", "base_uart3_clk", +> >> + "base_out_clk", "base_audio_clk", +> >> + "base_cgu_out0_clk","base_cgu_out1_clk"; > > > > Why do you need to use clock-indices? -> = - +> > Since the CGU can have up to 27 clock lines, but in this device not > all are used. So I use clock-indices so I don't need to have empty > entries in the clock-output-names array. I thought this was the > intended usage(?) -> = - +> > > Why do you need to use clock-output-names? If all of your clock > > consumers have nodes in DT then you can skip this and name them on the > > consuming side. See a further explanation here: > > http://lkml.kernel.org/r/<20150416192014.19585.9663@quantum> -> = - +> > Most of the clocks from the CGU goes to a CCU, but the CCU isn't the > real consumer. It's more like a clock router with a bunch of gates. -> = - +> > If you take a close look at the CCU driver you will notice that it > doesn't do clk_get on any of the clocks. My reason for doing this is > to not increase the usage counter on the CGU clock so that if there @@ -225,15 +191,12 @@ consumer devices have DT nodes of their own. Please look at the thread I linked to and let me know what you think about getting rid of the clock-output-names property. -> = - +> > Hope this makes sense. -> = - +> > > Also note that providing a clock consumer node in the examples section > > of the binding is helpful when reviewing. -> = - +> > I'll add a consumer example in the next version. Great. @@ -241,7 +204,6 @@ Great. Thanks, Mike -> = - +> > regards, > Joachim Eastwood diff --git a/a/content_digest b/N1/content_digest index 657180e..ab0fe0d 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,18 +2,10 @@ "ref\01430170693-28303-3-git-send-email-manabian@gmail.com\0" "ref\020150512221202.16410.2827@quantum\0" "ref\0CAGhQ9VyRjugLxscdL_wELbjMiDD3CFYJmsJAC_34wQeBmuxWjQ@mail.gmail.com\0" - "From\0Michael Turquette <mturquette@linaro.org>\0" - "Subject\0Re: [PATCH v2 2/4] doc: dt: add documentation for lpc1850-cgu clk driver\0" + "From\0mturquette@linaro.org (Michael Turquette)\0" + "Subject\0[PATCH v2 2/4] doc: dt: add documentation for lpc1850-cgu clk driver\0" "Date\0Thu, 21 May 2015 14:17:27 -0700\0" - "To\0Joachim Eastwood <manabian@gmail.com>" - "\0" - "Cc\0Stephen Boyd <sboyd@codeaurora.org>" - Arnd Bergmann <arnd@arndb.de> - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> - devicetree@vger.kernel.org - Ariel D'Alessandro <ariel.dalessandro@gmail.com> - " Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Quoting Joachim Eastwood (2015-05-13 00:57:18)\n" @@ -23,14 +15,11 @@ "> >>\n" "> >> Signed-off-by: Joachim Eastwood <manabian@gmail.com>\n" "> >> ---\n" - "> >> .../devicetree/bindings/clock/lpc1850-cgu.txt | 138 ++++++++++++=\n" - "+++++++++\n" + "> >> .../devicetree/bindings/clock/lpc1850-cgu.txt | 138 +++++++++++++++++++++\n" "> >> 1 file changed, 138 insertions(+)\n" - "> >> create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-cg=\n" - "u.txt\n" + "> >> create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-cgu.txt\n" "> >>\n" - "> >> diff --git a/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt b=\n" - "/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt\n" + "> >> diff --git a/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt b/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt\n" "> >> new file mode 100644\n" "> >> index 000000000000..0b278ca6aee7\n" "> >> --- /dev/null\n" @@ -83,27 +72,19 @@ "> >\n" "> >> +\n" "> >> +Number: Name: Description:\n" - "> >> + 0 BASE_SAFE_CLK Base safe clock (always on) fo=\n" - "r WWDT\n" + "> >> + 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT\n" "> >> + 1 BASE_USB0_CLK Base clock for USB0\n" - "> >> + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB su=\n" - "bsystem,\n" + "> >> + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem,\n" "> >> + SPI, and SGPIO\n" "> >> + 3 BASE_USB1_CLK Base clock for USB1\n" - "> >> + 4 BASE_CPU_CLK System base clock for ARM Cort=\n" - "ex-M core\n" - "> >> + and APB peripheral blocks #0 a=\n" - "nd #2\n" + "> >> + 4 BASE_CPU_CLK System base clock for ARM Cortex-M core\n" + "> >> + and APB peripheral blocks #0 and #2\n" "> >> + 5 BASE_SPIFI_CLK Base clock for SPIFI\n" "> >> + 6 BASE_SPI_CLK Base clock for SPI\n" - "> >> + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Re=\n" - "ceive clock\n" - "> >> + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Tr=\n" - "ansmit clock\n" - "> >> + 9 BASE_APB1_CLK Base clock for APB peripheral =\n" - "block # 1\n" - "> >> +10 BASE_APB3_CLK Base clock for APB peripheral =\n" - "block # 3\n" + "> >> + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock\n" + "> >> + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock\n" + "> >> + 9 BASE_APB1_CLK Base clock for APB peripheral block # 1\n" + "> >> +10 BASE_APB3_CLK Base clock for APB peripheral block # 3\n" "> >> +11 BASE_LCD_CLK Base clock for LCD\n" "> >> +12 BASE_ADCHS_CLK Base clock for ADCHS\n" "> >> +13 BASE_SDIO_CLK Base clock for SD/MMC\n" @@ -115,12 +96,9 @@ "> >> +19 BASE_UART3_CLK Base clock for UART3\n" "> >> +20 BASE_OUT_CLK Base clock for CLKOUT pin\n" "> >> +24-21 - Reserved\n" - "> >> +25 BASE_AUDIO_CLK Base clock for audio system (I=\n" - "2S)\n" - "> >> +26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock =\n" - "output\n" - "> >> +27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock =\n" - "output\n" + "> >> +25 BASE_AUDIO_CLK Base clock for audio system (I2S)\n" + "> >> +26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output\n" + "> >> +27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output\n" "> >> +\n" "> >> +BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx.\n" "> >> +BASE_ADCHS_CLK is only available on LPC4370.\n" @@ -131,96 +109,76 @@ "> >> +/ {\n" "> >> + clocks {\n" "> >> + xtal: xtal {\n" - "> >> + compatible =3D \"fixed-clock\";\n" - "> >> + #clock-cells =3D <0>;\n" - "> >> + clock-frequency =3D <12000000>;\n" + "> >> + compatible = \"fixed-clock\";\n" + "> >> + #clock-cells = <0>;\n" + "> >> + clock-frequency = <12000000>;\n" "> >> + };\n" "> >> +\n" "> >> + xtal32: xtal32 {\n" - "> >> + compatible =3D \"fixed-clock\";\n" - "> >> + #clock-cells =3D <0>;\n" - "> >> + clock-frequency =3D <32768>;\n" + "> >> + compatible = \"fixed-clock\";\n" + "> >> + #clock-cells = <0>;\n" + "> >> + clock-frequency = <32768>;\n" "> >> + };\n" "> >> +\n" "> >> + enet_rx_clk: enet_rx_clk {\n" - "> >> + compatible =3D \"fixed-clock\";\n" - "> >> + #clock-cells =3D <0>;\n" - "> >> + clock-frequency =3D <0>;\n" - "> >> + clock-output-names =3D \"enet_rx_clk\";\n" + "> >> + compatible = \"fixed-clock\";\n" + "> >> + #clock-cells = <0>;\n" + "> >> + clock-frequency = <0>;\n" + "> >> + clock-output-names = \"enet_rx_clk\";\n" "> >> + };\n" "> >> +\n" "> >> + enet_tx_clk: enet_tx_clk {\n" - "> >> + compatible =3D \"fixed-clock\";\n" - "> >> + #clock-cells =3D <0>;\n" - "> >> + clock-frequency =3D <0>;\n" - "> >> + clock-output-names =3D \"enet_tx_clk\";\n" + "> >> + compatible = \"fixed-clock\";\n" + "> >> + #clock-cells = <0>;\n" + "> >> + clock-frequency = <0>;\n" + "> >> + clock-output-names = \"enet_tx_clk\";\n" "> >> + };\n" "> >> +\n" "> >> + gp_clkin: gp_clkin {\n" - "> >> + compatible =3D \"fixed-clock\";\n" - "> >> + #clock-cells =3D <0>;\n" - "> >> + clock-frequency =3D <0>;\n" - "> >> + clock-output-names =3D \"gp_clkin\";\n" + "> >> + compatible = \"fixed-clock\";\n" + "> >> + #clock-cells = <0>;\n" + "> >> + clock-frequency = <0>;\n" + "> >> + clock-output-names = \"gp_clkin\";\n" "> >> + };\n" "> >> + };\n" "> >> +\n" "> >> + soc {\n" - "> >> + cgu: cgu@40050000 {\n" - "> >> + compatible =3D \"nxp,lpc1850-cgu\";\n" - "> >> + reg =3D <0x40050000 0x1000>;\n" - "> >> + #clock-cells =3D <1>;\n" - "> >> + clocks =3D <&xtal>, <&creg_clk 1>, <&enet_rx_c=\n" - "lk>, <&enet_tx_clk>, <&gp_clkin>;\n" - "> >> + clock-indices =3D <0>, <1>, <2>, <3>, <4>=\n" - ", <5>, <6>, <7>,\n" - "> >> + <8>, <9>, <10>, <11>, <12>, =\n" - "<13>, <14>, <15>,\n" - "> >> + <16>, <17>, <18>, <19>, <20>, =\n" - "<25>, <26>, <27>;\n" - "> >> + clock-output-names =3D \"base_safe_clk\", \"ba=\n" - "se_usb0_clk\",\n" - "> >> + \"base_periph_clk\", \"base=\n" - "_usb1_clk\",\n" - "> >> + \"base_cpu_clk\", \"base=\n" - "_spifi_clk\",\n" - "> >> + \"base_spi_clk\", \"base=\n" - "_phy_rx_clk\",\n" - "> >> + \"base_phy_tx_clk\", \"base=\n" - "_apb1_clk\",\n" - "> >> + \"base_apb3_clk\", \"base=\n" - "_lcd_clk\",\n" - "> >> + \"base_adchs_clk\", \"base=\n" - "_sdio_clk\",\n" - "> >> + \"base_ssp0_clk\", \"base=\n" - "_ssp1_clk\",\n" - "> >> + \"base_uart0_clk\", \"base=\n" - "_uart1_clk\",\n" - "> >> + \"base_uart2_clk\", \"base=\n" - "_uart3_clk\",\n" - "> >> + \"base_out_clk\", \"base=\n" - "_audio_clk\",\n" - "> >> + \"base_cgu_out0_clk\",\"base=\n" - "_cgu_out1_clk\";\n" + "> >> + cgu: cgu at 40050000 {\n" + "> >> + compatible = \"nxp,lpc1850-cgu\";\n" + "> >> + reg = <0x40050000 0x1000>;\n" + "> >> + #clock-cells = <1>;\n" + "> >> + clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;\n" + "> >> + clock-indices = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,\n" + "> >> + <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>,\n" + "> >> + <16>, <17>, <18>, <19>, <20>, <25>, <26>, <27>;\n" + "> >> + clock-output-names = \"base_safe_clk\", \"base_usb0_clk\",\n" + "> >> + \"base_periph_clk\", \"base_usb1_clk\",\n" + "> >> + \"base_cpu_clk\", \"base_spifi_clk\",\n" + "> >> + \"base_spi_clk\", \"base_phy_rx_clk\",\n" + "> >> + \"base_phy_tx_clk\", \"base_apb1_clk\",\n" + "> >> + \"base_apb3_clk\", \"base_lcd_clk\",\n" + "> >> + \"base_adchs_clk\", \"base_sdio_clk\",\n" + "> >> + \"base_ssp0_clk\", \"base_ssp1_clk\",\n" + "> >> + \"base_uart0_clk\", \"base_uart1_clk\",\n" + "> >> + \"base_uart2_clk\", \"base_uart3_clk\",\n" + "> >> + \"base_out_clk\", \"base_audio_clk\",\n" + "> >> + \"base_cgu_out0_clk\",\"base_cgu_out1_clk\";\n" "> >\n" "> > Why do you need to use clock-indices?\n" - "> =\n" - "\n" + "> \n" "> Since the CGU can have up to 27 clock lines, but in this device not\n" "> all are used. So I use clock-indices so I don't need to have empty\n" "> entries in the clock-output-names array. I thought this was the\n" "> intended usage(?)\n" - "> =\n" - "\n" + "> \n" "> > Why do you need to use clock-output-names? If all of your clock\n" "> > consumers have nodes in DT then you can skip this and name them on the\n" "> > consuming side. See a further explanation here:\n" "> > http://lkml.kernel.org/r/<20150416192014.19585.9663@quantum>\n" - "> =\n" - "\n" + "> \n" "> Most of the clocks from the CGU goes to a CCU, but the CCU isn't the\n" "> real consumer. It's more like a clock router with a bunch of gates.\n" - "> =\n" - "\n" + "> \n" "> If you take a close look at the CCU driver you will notice that it\n" "> doesn't do clk_get on any of the clocks. My reason for doing this is\n" "> to not increase the usage counter on the CGU clock so that if there\n" @@ -243,15 +201,12 @@ "linked to and let me know what you think about getting rid of the\n" "clock-output-names property.\n" "\n" - "> =\n" - "\n" + "> \n" "> Hope this makes sense.\n" - "> =\n" - "\n" + "> \n" "> > Also note that providing a clock consumer node in the examples section\n" "> > of the binding is helpful when reviewing.\n" - "> =\n" - "\n" + "> \n" "> I'll add a consumer example in the next version.\n" "\n" "Great.\n" @@ -259,9 +214,8 @@ "Thanks,\n" "Mike\n" "\n" - "> =\n" - "\n" + "> \n" "> regards,\n" > Joachim Eastwood -481842330c7387d6001f8ec78797bf209498f44099cac6a459cbd6af31a60854 +009e425e33f9cf16d9388f3c3a36572e11151d546618e63e1c257f21551401cf
diff --git a/a/1.txt b/N2/1.txt index d4413ad..7ddf95d 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -5,14 +5,11 @@ Quoting Joachim Eastwood (2015-05-13 00:57:18) > >> > >> Signed-off-by: Joachim Eastwood <manabian@gmail.com> > >> --- -> >> .../devicetree/bindings/clock/lpc1850-cgu.txt | 138 ++++++++++++= -+++++++++ +> >> .../devicetree/bindings/clock/lpc1850-cgu.txt | 138 +++++++++++++++++++++ > >> 1 file changed, 138 insertions(+) -> >> create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-cg= -u.txt +> >> create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-cgu.txt > >> -> >> diff --git a/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt b= -/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt +> >> diff --git a/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt b/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt > >> new file mode 100644 > >> index 000000000000..0b278ca6aee7 > >> --- /dev/null @@ -65,27 +62,19 @@ u.txt > > > >> + > >> +Number: Name: Description: -> >> + 0 BASE_SAFE_CLK Base safe clock (always on) fo= -r WWDT +> >> + 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT > >> + 1 BASE_USB0_CLK Base clock for USB0 -> >> + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB su= -bsystem, +> >> + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem, > >> + SPI, and SGPIO > >> + 3 BASE_USB1_CLK Base clock for USB1 -> >> + 4 BASE_CPU_CLK System base clock for ARM Cort= -ex-M core -> >> + and APB peripheral blocks #0 a= -nd #2 +> >> + 4 BASE_CPU_CLK System base clock for ARM Cortex-M core +> >> + and APB peripheral blocks #0 and #2 > >> + 5 BASE_SPIFI_CLK Base clock for SPIFI > >> + 6 BASE_SPI_CLK Base clock for SPI -> >> + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Re= -ceive clock -> >> + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Tr= -ansmit clock -> >> + 9 BASE_APB1_CLK Base clock for APB peripheral = -block # 1 -> >> +10 BASE_APB3_CLK Base clock for APB peripheral = -block # 3 +> >> + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock +> >> + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock +> >> + 9 BASE_APB1_CLK Base clock for APB peripheral block # 1 +> >> +10 BASE_APB3_CLK Base clock for APB peripheral block # 3 > >> +11 BASE_LCD_CLK Base clock for LCD > >> +12 BASE_ADCHS_CLK Base clock for ADCHS > >> +13 BASE_SDIO_CLK Base clock for SD/MMC @@ -97,12 +86,9 @@ block # 3 > >> +19 BASE_UART3_CLK Base clock for UART3 > >> +20 BASE_OUT_CLK Base clock for CLKOUT pin > >> +24-21 - Reserved -> >> +25 BASE_AUDIO_CLK Base clock for audio system (I= -2S) -> >> +26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock = -output -> >> +27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock = -output +> >> +25 BASE_AUDIO_CLK Base clock for audio system (I2S) +> >> +26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output +> >> +27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output > >> + > >> +BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx. > >> +BASE_ADCHS_CLK is only available on LPC4370. @@ -113,96 +99,76 @@ output > >> +/ { > >> + clocks { > >> + xtal: xtal { -> >> + compatible =3D "fixed-clock"; -> >> + #clock-cells =3D <0>; -> >> + clock-frequency =3D <12000000>; +> >> + compatible = "fixed-clock"; +> >> + #clock-cells = <0>; +> >> + clock-frequency = <12000000>; > >> + }; > >> + > >> + xtal32: xtal32 { -> >> + compatible =3D "fixed-clock"; -> >> + #clock-cells =3D <0>; -> >> + clock-frequency =3D <32768>; +> >> + compatible = "fixed-clock"; +> >> + #clock-cells = <0>; +> >> + clock-frequency = <32768>; > >> + }; > >> + > >> + enet_rx_clk: enet_rx_clk { -> >> + compatible =3D "fixed-clock"; -> >> + #clock-cells =3D <0>; -> >> + clock-frequency =3D <0>; -> >> + clock-output-names =3D "enet_rx_clk"; +> >> + compatible = "fixed-clock"; +> >> + #clock-cells = <0>; +> >> + clock-frequency = <0>; +> >> + clock-output-names = "enet_rx_clk"; > >> + }; > >> + > >> + enet_tx_clk: enet_tx_clk { -> >> + compatible =3D "fixed-clock"; -> >> + #clock-cells =3D <0>; -> >> + clock-frequency =3D <0>; -> >> + clock-output-names =3D "enet_tx_clk"; +> >> + compatible = "fixed-clock"; +> >> + #clock-cells = <0>; +> >> + clock-frequency = <0>; +> >> + clock-output-names = "enet_tx_clk"; > >> + }; > >> + > >> + gp_clkin: gp_clkin { -> >> + compatible =3D "fixed-clock"; -> >> + #clock-cells =3D <0>; -> >> + clock-frequency =3D <0>; -> >> + clock-output-names =3D "gp_clkin"; +> >> + compatible = "fixed-clock"; +> >> + #clock-cells = <0>; +> >> + clock-frequency = <0>; +> >> + clock-output-names = "gp_clkin"; > >> + }; > >> + }; > >> + > >> + soc { > >> + cgu: cgu@40050000 { -> >> + compatible =3D "nxp,lpc1850-cgu"; -> >> + reg =3D <0x40050000 0x1000>; -> >> + #clock-cells =3D <1>; -> >> + clocks =3D <&xtal>, <&creg_clk 1>, <&enet_rx_c= -lk>, <&enet_tx_clk>, <&gp_clkin>; -> >> + clock-indices =3D <0>, <1>, <2>, <3>, <4>= -, <5>, <6>, <7>, -> >> + <8>, <9>, <10>, <11>, <12>, = -<13>, <14>, <15>, -> >> + <16>, <17>, <18>, <19>, <20>, = -<25>, <26>, <27>; -> >> + clock-output-names =3D "base_safe_clk", "ba= -se_usb0_clk", -> >> + "base_periph_clk", "base= -_usb1_clk", -> >> + "base_cpu_clk", "base= -_spifi_clk", -> >> + "base_spi_clk", "base= -_phy_rx_clk", -> >> + "base_phy_tx_clk", "base= -_apb1_clk", -> >> + "base_apb3_clk", "base= -_lcd_clk", -> >> + "base_adchs_clk", "base= -_sdio_clk", -> >> + "base_ssp0_clk", "base= -_ssp1_clk", -> >> + "base_uart0_clk", "base= -_uart1_clk", -> >> + "base_uart2_clk", "base= -_uart3_clk", -> >> + "base_out_clk", "base= -_audio_clk", -> >> + "base_cgu_out0_clk","base= -_cgu_out1_clk"; +> >> + compatible = "nxp,lpc1850-cgu"; +> >> + reg = <0x40050000 0x1000>; +> >> + #clock-cells = <1>; +> >> + clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; +> >> + clock-indices = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, +> >> + <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, +> >> + <16>, <17>, <18>, <19>, <20>, <25>, <26>, <27>; +> >> + clock-output-names = "base_safe_clk", "base_usb0_clk", +> >> + "base_periph_clk", "base_usb1_clk", +> >> + "base_cpu_clk", "base_spifi_clk", +> >> + "base_spi_clk", "base_phy_rx_clk", +> >> + "base_phy_tx_clk", "base_apb1_clk", +> >> + "base_apb3_clk", "base_lcd_clk", +> >> + "base_adchs_clk", "base_sdio_clk", +> >> + "base_ssp0_clk", "base_ssp1_clk", +> >> + "base_uart0_clk", "base_uart1_clk", +> >> + "base_uart2_clk", "base_uart3_clk", +> >> + "base_out_clk", "base_audio_clk", +> >> + "base_cgu_out0_clk","base_cgu_out1_clk"; > > > > Why do you need to use clock-indices? -> = - +> > Since the CGU can have up to 27 clock lines, but in this device not > all are used. So I use clock-indices so I don't need to have empty > entries in the clock-output-names array. I thought this was the > intended usage(?) -> = - +> > > Why do you need to use clock-output-names? If all of your clock > > consumers have nodes in DT then you can skip this and name them on the > > consuming side. See a further explanation here: > > http://lkml.kernel.org/r/<20150416192014.19585.9663@quantum> -> = - +> > Most of the clocks from the CGU goes to a CCU, but the CCU isn't the > real consumer. It's more like a clock router with a bunch of gates. -> = - +> > If you take a close look at the CCU driver you will notice that it > doesn't do clk_get on any of the clocks. My reason for doing this is > to not increase the usage counter on the CGU clock so that if there @@ -225,15 +191,12 @@ consumer devices have DT nodes of their own. Please look at the thread I linked to and let me know what you think about getting rid of the clock-output-names property. -> = - +> > Hope this makes sense. -> = - +> > > Also note that providing a clock consumer node in the examples section > > of the binding is helpful when reviewing. -> = - +> > I'll add a consumer example in the next version. Great. @@ -241,7 +204,6 @@ Great. Thanks, Mike -> = - +> > regards, > Joachim Eastwood diff --git a/a/content_digest b/N2/content_digest index 657180e..e62e6f9 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -5,15 +5,14 @@ "From\0Michael Turquette <mturquette@linaro.org>\0" "Subject\0Re: [PATCH v2 2/4] doc: dt: add documentation for lpc1850-cgu clk driver\0" "Date\0Thu, 21 May 2015 14:17:27 -0700\0" - "To\0Joachim Eastwood <manabian@gmail.com>" - "\0" - "Cc\0Stephen Boyd <sboyd@codeaurora.org>" + "To\0Joachim Eastwood <manabian@gmail.com>\0" + "Cc\0devicetree@vger.kernel.org" Arnd Bergmann <arnd@arndb.de> - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> - devicetree@vger.kernel.org + Stephen Boyd <sboyd@codeaurora.org> Ariel D'Alessandro <ariel.dalessandro@gmail.com> - " Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>\0" + Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> + linux-clk@vger.kernel.org + " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" "\00:1\0" "b\0" "Quoting Joachim Eastwood (2015-05-13 00:57:18)\n" @@ -23,14 +22,11 @@ "> >>\n" "> >> Signed-off-by: Joachim Eastwood <manabian@gmail.com>\n" "> >> ---\n" - "> >> .../devicetree/bindings/clock/lpc1850-cgu.txt | 138 ++++++++++++=\n" - "+++++++++\n" + "> >> .../devicetree/bindings/clock/lpc1850-cgu.txt | 138 +++++++++++++++++++++\n" "> >> 1 file changed, 138 insertions(+)\n" - "> >> create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-cg=\n" - "u.txt\n" + "> >> create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-cgu.txt\n" "> >>\n" - "> >> diff --git a/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt b=\n" - "/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt\n" + "> >> diff --git a/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt b/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt\n" "> >> new file mode 100644\n" "> >> index 000000000000..0b278ca6aee7\n" "> >> --- /dev/null\n" @@ -83,27 +79,19 @@ "> >\n" "> >> +\n" "> >> +Number: Name: Description:\n" - "> >> + 0 BASE_SAFE_CLK Base safe clock (always on) fo=\n" - "r WWDT\n" + "> >> + 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT\n" "> >> + 1 BASE_USB0_CLK Base clock for USB0\n" - "> >> + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB su=\n" - "bsystem,\n" + "> >> + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem,\n" "> >> + SPI, and SGPIO\n" "> >> + 3 BASE_USB1_CLK Base clock for USB1\n" - "> >> + 4 BASE_CPU_CLK System base clock for ARM Cort=\n" - "ex-M core\n" - "> >> + and APB peripheral blocks #0 a=\n" - "nd #2\n" + "> >> + 4 BASE_CPU_CLK System base clock for ARM Cortex-M core\n" + "> >> + and APB peripheral blocks #0 and #2\n" "> >> + 5 BASE_SPIFI_CLK Base clock for SPIFI\n" "> >> + 6 BASE_SPI_CLK Base clock for SPI\n" - "> >> + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Re=\n" - "ceive clock\n" - "> >> + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Tr=\n" - "ansmit clock\n" - "> >> + 9 BASE_APB1_CLK Base clock for APB peripheral =\n" - "block # 1\n" - "> >> +10 BASE_APB3_CLK Base clock for APB peripheral =\n" - "block # 3\n" + "> >> + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock\n" + "> >> + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock\n" + "> >> + 9 BASE_APB1_CLK Base clock for APB peripheral block # 1\n" + "> >> +10 BASE_APB3_CLK Base clock for APB peripheral block # 3\n" "> >> +11 BASE_LCD_CLK Base clock for LCD\n" "> >> +12 BASE_ADCHS_CLK Base clock for ADCHS\n" "> >> +13 BASE_SDIO_CLK Base clock for SD/MMC\n" @@ -115,12 +103,9 @@ "> >> +19 BASE_UART3_CLK Base clock for UART3\n" "> >> +20 BASE_OUT_CLK Base clock for CLKOUT pin\n" "> >> +24-21 - Reserved\n" - "> >> +25 BASE_AUDIO_CLK Base clock for audio system (I=\n" - "2S)\n" - "> >> +26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock =\n" - "output\n" - "> >> +27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock =\n" - "output\n" + "> >> +25 BASE_AUDIO_CLK Base clock for audio system (I2S)\n" + "> >> +26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output\n" + "> >> +27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output\n" "> >> +\n" "> >> +BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx.\n" "> >> +BASE_ADCHS_CLK is only available on LPC4370.\n" @@ -131,96 +116,76 @@ "> >> +/ {\n" "> >> + clocks {\n" "> >> + xtal: xtal {\n" - "> >> + compatible =3D \"fixed-clock\";\n" - "> >> + #clock-cells =3D <0>;\n" - "> >> + clock-frequency =3D <12000000>;\n" + "> >> + compatible = \"fixed-clock\";\n" + "> >> + #clock-cells = <0>;\n" + "> >> + clock-frequency = <12000000>;\n" "> >> + };\n" "> >> +\n" "> >> + xtal32: xtal32 {\n" - "> >> + compatible =3D \"fixed-clock\";\n" - "> >> + #clock-cells =3D <0>;\n" - "> >> + clock-frequency =3D <32768>;\n" + "> >> + compatible = \"fixed-clock\";\n" + "> >> + #clock-cells = <0>;\n" + "> >> + clock-frequency = <32768>;\n" "> >> + };\n" "> >> +\n" "> >> + enet_rx_clk: enet_rx_clk {\n" - "> >> + compatible =3D \"fixed-clock\";\n" - "> >> + #clock-cells =3D <0>;\n" - "> >> + clock-frequency =3D <0>;\n" - "> >> + clock-output-names =3D \"enet_rx_clk\";\n" + "> >> + compatible = \"fixed-clock\";\n" + "> >> + #clock-cells = <0>;\n" + "> >> + clock-frequency = <0>;\n" + "> >> + clock-output-names = \"enet_rx_clk\";\n" "> >> + };\n" "> >> +\n" "> >> + enet_tx_clk: enet_tx_clk {\n" - "> >> + compatible =3D \"fixed-clock\";\n" - "> >> + #clock-cells =3D <0>;\n" - "> >> + clock-frequency =3D <0>;\n" - "> >> + clock-output-names =3D \"enet_tx_clk\";\n" + "> >> + compatible = \"fixed-clock\";\n" + "> >> + #clock-cells = <0>;\n" + "> >> + clock-frequency = <0>;\n" + "> >> + clock-output-names = \"enet_tx_clk\";\n" "> >> + };\n" "> >> +\n" "> >> + gp_clkin: gp_clkin {\n" - "> >> + compatible =3D \"fixed-clock\";\n" - "> >> + #clock-cells =3D <0>;\n" - "> >> + clock-frequency =3D <0>;\n" - "> >> + clock-output-names =3D \"gp_clkin\";\n" + "> >> + compatible = \"fixed-clock\";\n" + "> >> + #clock-cells = <0>;\n" + "> >> + clock-frequency = <0>;\n" + "> >> + clock-output-names = \"gp_clkin\";\n" "> >> + };\n" "> >> + };\n" "> >> +\n" "> >> + soc {\n" "> >> + cgu: cgu@40050000 {\n" - "> >> + compatible =3D \"nxp,lpc1850-cgu\";\n" - "> >> + reg =3D <0x40050000 0x1000>;\n" - "> >> + #clock-cells =3D <1>;\n" - "> >> + clocks =3D <&xtal>, <&creg_clk 1>, <&enet_rx_c=\n" - "lk>, <&enet_tx_clk>, <&gp_clkin>;\n" - "> >> + clock-indices =3D <0>, <1>, <2>, <3>, <4>=\n" - ", <5>, <6>, <7>,\n" - "> >> + <8>, <9>, <10>, <11>, <12>, =\n" - "<13>, <14>, <15>,\n" - "> >> + <16>, <17>, <18>, <19>, <20>, =\n" - "<25>, <26>, <27>;\n" - "> >> + clock-output-names =3D \"base_safe_clk\", \"ba=\n" - "se_usb0_clk\",\n" - "> >> + \"base_periph_clk\", \"base=\n" - "_usb1_clk\",\n" - "> >> + \"base_cpu_clk\", \"base=\n" - "_spifi_clk\",\n" - "> >> + \"base_spi_clk\", \"base=\n" - "_phy_rx_clk\",\n" - "> >> + \"base_phy_tx_clk\", \"base=\n" - "_apb1_clk\",\n" - "> >> + \"base_apb3_clk\", \"base=\n" - "_lcd_clk\",\n" - "> >> + \"base_adchs_clk\", \"base=\n" - "_sdio_clk\",\n" - "> >> + \"base_ssp0_clk\", \"base=\n" - "_ssp1_clk\",\n" - "> >> + \"base_uart0_clk\", \"base=\n" - "_uart1_clk\",\n" - "> >> + \"base_uart2_clk\", \"base=\n" - "_uart3_clk\",\n" - "> >> + \"base_out_clk\", \"base=\n" - "_audio_clk\",\n" - "> >> + \"base_cgu_out0_clk\",\"base=\n" - "_cgu_out1_clk\";\n" + "> >> + compatible = \"nxp,lpc1850-cgu\";\n" + "> >> + reg = <0x40050000 0x1000>;\n" + "> >> + #clock-cells = <1>;\n" + "> >> + clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;\n" + "> >> + clock-indices = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,\n" + "> >> + <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>,\n" + "> >> + <16>, <17>, <18>, <19>, <20>, <25>, <26>, <27>;\n" + "> >> + clock-output-names = \"base_safe_clk\", \"base_usb0_clk\",\n" + "> >> + \"base_periph_clk\", \"base_usb1_clk\",\n" + "> >> + \"base_cpu_clk\", \"base_spifi_clk\",\n" + "> >> + \"base_spi_clk\", \"base_phy_rx_clk\",\n" + "> >> + \"base_phy_tx_clk\", \"base_apb1_clk\",\n" + "> >> + \"base_apb3_clk\", \"base_lcd_clk\",\n" + "> >> + \"base_adchs_clk\", \"base_sdio_clk\",\n" + "> >> + \"base_ssp0_clk\", \"base_ssp1_clk\",\n" + "> >> + \"base_uart0_clk\", \"base_uart1_clk\",\n" + "> >> + \"base_uart2_clk\", \"base_uart3_clk\",\n" + "> >> + \"base_out_clk\", \"base_audio_clk\",\n" + "> >> + \"base_cgu_out0_clk\",\"base_cgu_out1_clk\";\n" "> >\n" "> > Why do you need to use clock-indices?\n" - "> =\n" - "\n" + "> \n" "> Since the CGU can have up to 27 clock lines, but in this device not\n" "> all are used. So I use clock-indices so I don't need to have empty\n" "> entries in the clock-output-names array. I thought this was the\n" "> intended usage(?)\n" - "> =\n" - "\n" + "> \n" "> > Why do you need to use clock-output-names? If all of your clock\n" "> > consumers have nodes in DT then you can skip this and name them on the\n" "> > consuming side. See a further explanation here:\n" "> > http://lkml.kernel.org/r/<20150416192014.19585.9663@quantum>\n" - "> =\n" - "\n" + "> \n" "> Most of the clocks from the CGU goes to a CCU, but the CCU isn't the\n" "> real consumer. It's more like a clock router with a bunch of gates.\n" - "> =\n" - "\n" + "> \n" "> If you take a close look at the CCU driver you will notice that it\n" "> doesn't do clk_get on any of the clocks. My reason for doing this is\n" "> to not increase the usage counter on the CGU clock so that if there\n" @@ -243,15 +208,12 @@ "linked to and let me know what you think about getting rid of the\n" "clock-output-names property.\n" "\n" - "> =\n" - "\n" + "> \n" "> Hope this makes sense.\n" - "> =\n" - "\n" + "> \n" "> > Also note that providing a clock consumer node in the examples section\n" "> > of the binding is helpful when reviewing.\n" - "> =\n" - "\n" + "> \n" "> I'll add a consumer example in the next version.\n" "\n" "Great.\n" @@ -259,9 +221,8 @@ "Thanks,\n" "Mike\n" "\n" - "> =\n" - "\n" + "> \n" "> regards,\n" > Joachim Eastwood -481842330c7387d6001f8ec78797bf209498f44099cac6a459cbd6af31a60854 +dc3b24bda4f3106adc7cd479c8a2cea9a39118e2b34997ca67170566b5fd25c0
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.