From: Cyril Chemparathy <cchemparathy@ezchip.com>
To: Thomas Monjalon <thomas.monjalon@6wind.com>
Cc: dev@dpdk.org
Subject: Re: [PATCH v2 12/12] mk: introduce Tilera Tile architecture
Date: Fri, 22 May 2015 12:42:39 -0400 [thread overview]
Message-ID: <20150522124239.5c51bf3a@cchemparathy-ubuntu> (raw)
In-Reply-To: <1666029.giUU904B6N@xps13>
On Fri, 22 May 2015 18:03:04 +0200
Thomas Monjalon <thomas.monjalon@6wind.com> wrote:
> Hi,
>
> 2015-01-06 14:53, Zhigang Lu:
> > Add defconfig and rte.vars.mk files for Tile architecture.
> >
> > Signed-off-by: Zhigang Lu <zlu@ezchip.com>
> > Signed-off-by: Cyril Chemparathy <cchemparathy@ezchip.com>
>
> This series is pending without having any comments.
> So it should be accepted and merged.
>
I'm working on a refresh to the latest master. In the process, I've
simplified most of the patches down to bare essentials.
Since the TILE-Gx platform is a strict alignment machine, we need
alignment related fixes that have been submitted previously (see
http://www.dpdk.org/ml/archives/dev/2015-April/017090.html). These are
based on relatively recent contents of master, and therefore should be
ready to merge once we go through the review cycle. Would you mind
taking a look at these?
> Do you accept to be the maintainer of Tile architecture?
> If you agree, please respin this series with a cover letter (it was
> missing in this v2) and update the MAINTAINERS file.
>
Sure. We'll internally figure out the appropriate maintainer and
include this in the next round of patches.
Thanks
-- Cyril.
prev parent reply other threads:[~2015-05-22 16:42 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1420527230-17037-1-git-send-email-zlu@ezchip.com>
[not found] ` <1420527230-17037-1-git-send-email-zlu-d5a29ZRxExrQT0dZR+AlfA@public.gmane.org>
2015-01-06 6:53 ` [PATCH v2 01/12] eal/tile: add atomic operations for TileGx Zhigang Lu
2015-01-06 6:53 ` [PATCH v2 02/12] eal/tile: add byte order " Zhigang Lu
2015-01-06 6:53 ` [PATCH v2 03/12] eal/tile: add spinlock " Zhigang Lu
2015-01-06 6:53 ` [PATCH v2 04/12] eal/tile: add prefetch " Zhigang Lu
2015-01-06 6:53 ` [PATCH v2 05/12] eal/tile: add memcpy " Zhigang Lu
2015-01-06 6:53 ` [PATCH v2 06/12] eal/tile: add cycle " Zhigang Lu
2015-01-06 6:53 ` [PATCH v2 07/12] eal: split vector operations to architecture specific Zhigang Lu
2015-01-06 6:53 ` [PATCH v2 08/12] eal/tile: add vector operations for TileGx Zhigang Lu
2015-01-06 6:53 ` [PATCH v2 09/12] eal/tile: add CPU flags " Zhigang Lu
2015-01-06 6:53 ` [PATCH v2 10/12] app/test: remove architecture specific code from cpuflags test Zhigang Lu
2015-01-06 6:53 ` [PATCH v2 11/12] eal: allow empty set of compile time cpuflags Zhigang Lu
2015-01-06 6:53 ` [PATCH v2 12/12] mk: introduce Tilera Tile architecture Zhigang Lu
2015-05-22 16:03 ` Thomas Monjalon
2015-05-22 16:42 ` Cyril Chemparathy [this message]
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