From: Pavel Machek <pavel@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCHv3 2/3] driver/ddr/altera/: Add the sdram calibration portion
Date: Mon, 25 May 2015 14:37:50 +0200 [thread overview]
Message-ID: <20150525123750.GD9943@amd> (raw)
In-Reply-To: <1431977809-23652-3-git-send-email-dinguyen@opensource.altera.com>
Hi!
> +/******************************************************************************
> + ******************************************************************************
> + ** NOTE: Special Rules for Globale Variables **
They are global, not globale.
> + ** All global variables that are explicitly initialized (including **
> + ** explicitly initialized to zero), are only initialized once, during **
> + ** configuration time, and not again on reset. This means that they **
> + ** preserve their current contents across resets, which is needed for some **
> + ** special cases involving communication with external modules. In **
> + ** addition, this avoids paying the price to have the memory initialized, **
> + ** even for zeroed data, provided it is explicitly set to zero in the code, **
> + ** and doesn't rely on implicit initialization. **
> + ******************************************************************************
> +
Is this sane thing to do? How does it work for variables in other
sources?
What penalty is there for just redoing initialization from scratch
each time?
Thanks,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
next prev parent reply other threads:[~2015-05-25 12:37 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-18 19:36 [U-Boot] [PATCHv3 0/3] drivers/ddr/altera: Add the DDR controller driver for SoCFPGA dinguyen at opensource.altera.com
2015-05-18 19:36 ` [U-Boot] [PATCHv3 1/3] driver/ddr/altera: Add DDR driver for Altera's SDRAM controller dinguyen at opensource.altera.com
2015-05-21 23:33 ` Marek Vasut
2015-05-18 19:36 ` [U-Boot] [PATCHv3 2/3] driver/ddr/altera/: Add the sdram calibration portion dinguyen at opensource.altera.com
2015-05-21 23:35 ` Marek Vasut
2015-05-22 2:43 ` Dinh Nguyen
2015-05-22 6:39 ` Stefan Roese
2015-05-22 10:36 ` Marek Vasut
2015-05-25 12:37 ` Pavel Machek [this message]
2015-05-25 13:23 ` Wolfgang Denk
2015-05-28 15:41 ` Dinh Nguyen
2015-05-28 18:18 ` Marek Vasut
2015-05-29 15:24 ` Dinh Nguyen
2015-06-01 13:17 ` Marek Vasut
2015-05-28 15:49 ` Dinh Nguyen
2015-05-18 19:36 ` [U-Boot] [PATCHv3 3/3] arm: socfpga: enable the Altera SDRAM controller driver dinguyen at opensource.altera.com
2015-05-21 23:35 ` Marek Vasut
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