From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wi0-f175.google.com (mail-wi0-f175.google.com. [209.85.212.175]) by gmr-mx.google.com with ESMTPS id u10si511118wif.1.2015.05.26.05.39.48 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 May 2015 05:39:48 -0700 (PDT) Received: by wicmx19 with SMTP id mx19so63524434wic.0 for ; Tue, 26 May 2015 05:39:48 -0700 (PDT) Date: Tue, 26 May 2015 13:39:43 +0100 From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, daniel.lezcano@linaro.org, tglx@linutronix.de, wim@iguana.be, a.zummo@towertech.it, linux-watchdog@vger.kernel.org, rtc-linux@googlegroups.com, linux@roeck-us.net Cc: kernel@stlinux.com Subject: [rtc-linux] [PATCH v2.1 02/12] clocksource: sti: Provide support for the ST LPC Clocksource IP Message-ID: <20150526123943.GI11677@x1> References: <1431435500-22899-1-git-send-email-lee.jones@linaro.org> <1431435500-22899-3-git-send-email-lee.jones@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 In-Reply-To: <1431435500-22899-3-git-send-email-lee.jones@linaro.org> Reply-To: rtc-linux@googlegroups.com List-ID: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , clocksource: sti: Provide support for the ST LPC Clocksource IP This IP is shared with Watchdog and RTC functionality. All 3 of these devices are mutually exclusive from one another i.e. Only 1 IP can be used at any given time. We use the device-driver model combined with a DT 'mode' property to enforce this. The ST LPC Clocksource IP can be used as the system (tick) timer. Signed-off-by: Lee Jones diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 68161f7..01a07a6 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -250,4 +250,13 @@ config CLKSRC_PXA help This enables OST0 support available on PXA and SA-11x0 platforms. + +config CLKSRC_ST_LPC + bool + depends on ARCH_STI + select CLKSRC_OF if OF + help + Enable this option to use the Low Power controller timer + as clocksource. + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 752d5c7..e08da4d 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -51,3 +51,4 @@ obj-$(CONFIG_ARCH_INTEGRATOR_AP) +=3D timer-integrator-ap= .o obj-$(CONFIG_CLKSRC_VERSATILE) +=3D versatile.o obj-$(CONFIG_CLKSRC_MIPS_GIC) +=3D mips-gic-timer.o obj-$(CONFIG_ASM9260_TIMER) +=3D asm9260_timer.o +obj-$(CONFIG_CLKSRC_ST_LPC) +=3D clksrc_st_lpc.o diff --git a/drivers/clocksource/clksrc_st_lpc.c b/drivers/clocksource/clks= rc_st_lpc.c new file mode 100644 index 0000000..f38cf33 --- /dev/null +++ b/drivers/clocksource/clksrc_st_lpc.c @@ -0,0 +1,123 @@ +/* + * Clocksource using the Low Power Timer found in the Low Power Controller= (LPC) + * + * Copyright (C) 2015 STMicroelectronics =E2=80=93 All Rights Reserved + * + * Author(s): Francesco Virlinzi + * Ajit Pal Singh + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include + +#include + +/* Low Power Timer */ +#define LPC_LPT_LSB_OFF 0x400 +#define LPC_LPT_MSB_OFF 0x404 +#define LPC_LPT_START_OFF 0x408 + +static struct st_clksrc_ddata { + struct clk *clk; + void __iomem *base; +} ddata; + +static void __init st_clksrc_reset(void) +{ + writel_relaxed(0, ddata.base + LPC_LPT_START_OFF); + writel_relaxed(0, ddata.base + LPC_LPT_MSB_OFF); + writel_relaxed(0, ddata.base + LPC_LPT_LSB_OFF); + writel_relaxed(1, ddata.base + LPC_LPT_START_OFF); +} + +static int __init st_clksrc_init(void) +{ + unsigned long rate; + int ret; + + st_clksrc_reset(); + + rate =3D clk_get_rate(ddata.clk); + + ret =3D clocksource_mmio_init(ddata.base + LPC_LPT_LSB_OFF, + "clksrc-st-lpc", rate, 300, 32, + clocksource_mmio_readl_up); + if (ret) { + pr_err("clksrc-st-lpc: Failed to register clocksource\n"); + return ret; + } + + return 0; +} + +static int __init st_clksrc_setup_clk(struct device_node *np) +{ + struct clk *clk; + + clk =3D of_clk_get(np, 0); + if (IS_ERR(clk)) { + pr_err("clksrc-st-lpc: Failed to get LPC clock\n"); + return PTR_ERR(clk); + } + + if (clk_prepare_enable(clk)) { + pr_err("clksrc-st-lpc: Failed to enable LPC clock\n"); + return -EINVAL; + } + + if (!clk_get_rate(clk)) { + pr_err("clksrc-st-lpc: Failed to get LPC clock rate\n"); + clk_disable_unprepare(clk); + return -EINVAL; + } + + ddata.clk =3D clk; + + return 0; +} + +static void __init st_clksrc_of_register(struct device_node *np) +{ + int ret; + uint32_t mode; + + ret =3D of_property_read_u32(np, "st,lpc-mode", &mode); + if (ret) { + pr_err("clksrc-st-lpc: An LPC mode must be provided\n"); + return; + } + + /* LPC can either run as a Clocksource or in RTC or WDT mode */ + if (mode !=3D ST_LPC_MODE_CLKSRC) + return; + + ddata.base =3D of_iomap(np, 0); + if (!ddata.base) { + pr_err("clksrc-st-lpc: Unable to map iomem\n"); + return; + } + + if (st_clksrc_setup_clk(np)) { + iounmap(ddata.base); + return; + } + + if (st_clksrc_init()) { + clk_disable_unprepare(ddata.clk); + clk_put(ddata.clk); + iounmap(ddata.base); + return; + } + + pr_info("clksrc-st-lpc: clocksource initialised - running @ %luHz\n", + clk_get_rate(ddata.clk)); +} +CLOCKSOURCE_OF_DECLARE(ddata, "st,stih407-lpc", st_clksrc_of_register); --=20 --=20 You received this message because you are subscribed to "rtc-linux". Membership options at http://groups.google.com/group/rtc-linux . Please read http://groups.google.com/group/rtc-linux/web/checklist before submitting a driver. ---=20 You received this message because you are subscribed to the Google Groups "= rtc-linux" group. To unsubscribe from this group and stop receiving emails from it, send an e= mail to rtc-linux+unsubscribe@googlegroups.com. For more options, visit https://groups.google.com/d/optout. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mail-wg0-f41.google.com ([74.125.82.41]:35584 "EHLO mail-wg0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752641AbbEZMrO (ORCPT ); Tue, 26 May 2015 08:47:14 -0400 Received: by wgme6 with SMTP id e6so27548495wgm.2 for ; Tue, 26 May 2015 05:45:11 -0700 (PDT) Date: Tue, 26 May 2015 13:39:43 +0100 From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, daniel.lezcano@linaro.org, tglx@linutronix.de, wim@iguana.be, a.zummo@towertech.it, linux-watchdog@vger.kernel.org, rtc-linux@googlegroups.com, linux@roeck-us.net Cc: kernel@stlinux.com Subject: [PATCH v2.1 02/12] clocksource: sti: Provide support for the ST LPC Clocksource IP Message-ID: <20150526123943.GI11677@x1> References: <1431435500-22899-1-git-send-email-lee.jones@linaro.org> <1431435500-22899-3-git-send-email-lee.jones@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1431435500-22899-3-git-send-email-lee.jones@linaro.org> Sender: linux-watchdog-owner@vger.kernel.org List-Id: linux-watchdog@vger.kernel.org Content-Transfer-Encoding: quoted-printable clocksource: sti: Provide support for the ST LPC Clocksource IP This IP is shared with Watchdog and RTC functionality. All 3 of these devices are mutually exclusive from one another i.e. Only 1 IP can be used at any given time. We use the device-driver model combined with a DT 'mode' property to enforce this. The ST LPC Clocksource IP can be used as the system (tick) timer. Signed-off-by: Lee Jones diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 68161f7..01a07a6 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -250,4 +250,13 @@ config CLKSRC_PXA help This enables OST0 support available on PXA and SA-11x0 platforms. + +config CLKSRC_ST_LPC + bool + depends on ARCH_STI + select CLKSRC_OF if OF + help + Enable this option to use the Low Power controller timer + as clocksource. + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 752d5c7..e08da4d 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -51,3 +51,4 @@ obj-$(CONFIG_ARCH_INTEGRATOR_AP) +=3D timer-integrator-= ap.o obj-$(CONFIG_CLKSRC_VERSATILE) +=3D versatile.o obj-$(CONFIG_CLKSRC_MIPS_GIC) +=3D mips-gic-timer.o obj-$(CONFIG_ASM9260_TIMER) +=3D asm9260_timer.o +obj-$(CONFIG_CLKSRC_ST_LPC) +=3D clksrc_st_lpc.o diff --git a/drivers/clocksource/clksrc_st_lpc.c b/drivers/clocksource/cl= ksrc_st_lpc.c new file mode 100644 index 0000000..f38cf33 --- /dev/null +++ b/drivers/clocksource/clksrc_st_lpc.c @@ -0,0 +1,123 @@ +/* + * Clocksource using the Low Power Timer found in the Low Power Controll= er (LPC) + * + * Copyright (C) 2015 STMicroelectronics =E2=80=93 All Rights Reserved + * + * Author(s): Francesco Virlinzi + * Ajit Pal Singh + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include + +#include + +/* Low Power Timer */ +#define LPC_LPT_LSB_OFF 0x400 +#define LPC_LPT_MSB_OFF 0x404 +#define LPC_LPT_START_OFF 0x408 + +static struct st_clksrc_ddata { + struct clk *clk; + void __iomem *base; +} ddata; + +static void __init st_clksrc_reset(void) +{ + writel_relaxed(0, ddata.base + LPC_LPT_START_OFF); + writel_relaxed(0, ddata.base + LPC_LPT_MSB_OFF); + writel_relaxed(0, ddata.base + LPC_LPT_LSB_OFF); + writel_relaxed(1, ddata.base + LPC_LPT_START_OFF); +} + +static int __init st_clksrc_init(void) +{ + unsigned long rate; + int ret; + + st_clksrc_reset(); + + rate =3D clk_get_rate(ddata.clk); + + ret =3D clocksource_mmio_init(ddata.base + LPC_LPT_LSB_OFF, + "clksrc-st-lpc", rate, 300, 32, + clocksource_mmio_readl_up); + if (ret) { + pr_err("clksrc-st-lpc: Failed to register clocksource\n"); + return ret; + } + + return 0; +} + +static int __init st_clksrc_setup_clk(struct device_node *np) +{ + struct clk *clk; + + clk =3D of_clk_get(np, 0); + if (IS_ERR(clk)) { + pr_err("clksrc-st-lpc: Failed to get LPC clock\n"); + return PTR_ERR(clk); + } + + if (clk_prepare_enable(clk)) { + pr_err("clksrc-st-lpc: Failed to enable LPC clock\n"); + return -EINVAL; + } + + if (!clk_get_rate(clk)) { + pr_err("clksrc-st-lpc: Failed to get LPC clock rate\n"); + clk_disable_unprepare(clk); + return -EINVAL; + } + + ddata.clk =3D clk; + + return 0; +} + +static void __init st_clksrc_of_register(struct device_node *np) +{ + int ret; + uint32_t mode; + + ret =3D of_property_read_u32(np, "st,lpc-mode", &mode); + if (ret) { + pr_err("clksrc-st-lpc: An LPC mode must be provided\n"); + return; + } + + /* LPC can either run as a Clocksource or in RTC or WDT mode */ + if (mode !=3D ST_LPC_MODE_CLKSRC) + return; + + ddata.base =3D of_iomap(np, 0); + if (!ddata.base) { + pr_err("clksrc-st-lpc: Unable to map iomem\n"); + return; + } + + if (st_clksrc_setup_clk(np)) { + iounmap(ddata.base); + return; + } + + if (st_clksrc_init()) { + clk_disable_unprepare(ddata.clk); + clk_put(ddata.clk); + iounmap(ddata.base); + return; + } + + pr_info("clksrc-st-lpc: clocksource initialised - running @ %luHz\n", + clk_get_rate(ddata.clk)); +} +CLOCKSOURCE_OF_DECLARE(ddata, "st,stih407-lpc", st_clksrc_of_register); -- To unsubscribe from this list: send the line "unsubscribe linux-watchdog"= in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: lee.jones@linaro.org (Lee Jones) Date: Tue, 26 May 2015 13:39:43 +0100 Subject: [PATCH v2.1 02/12] clocksource: sti: Provide support for the ST LPC Clocksource IP In-Reply-To: <1431435500-22899-3-git-send-email-lee.jones@linaro.org> References: <1431435500-22899-1-git-send-email-lee.jones@linaro.org> <1431435500-22899-3-git-send-email-lee.jones@linaro.org> Message-ID: <20150526123943.GI11677@x1> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org clocksource: sti: Provide support for the ST LPC Clocksource IP This IP is shared with Watchdog and RTC functionality. All 3 of these devices are mutually exclusive from one another i.e. Only 1 IP can be used at any given time. We use the device-driver model combined with a DT 'mode' property to enforce this. The ST LPC Clocksource IP can be used as the system (tick) timer. Signed-off-by: Lee Jones diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 68161f7..01a07a6 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -250,4 +250,13 @@ config CLKSRC_PXA help This enables OST0 support available on PXA and SA-11x0 platforms. + +config CLKSRC_ST_LPC + bool + depends on ARCH_STI + select CLKSRC_OF if OF + help + Enable this option to use the Low Power controller timer + as clocksource. + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 752d5c7..e08da4d 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -51,3 +51,4 @@ obj-$(CONFIG_ARCH_INTEGRATOR_AP) += timer-integrator-ap.o obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o +obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o diff --git a/drivers/clocksource/clksrc_st_lpc.c b/drivers/clocksource/clksrc_st_lpc.c new file mode 100644 index 0000000..f38cf33 --- /dev/null +++ b/drivers/clocksource/clksrc_st_lpc.c @@ -0,0 +1,123 @@ +/* + * Clocksource using the Low Power Timer found in the Low Power Controller (LPC) + * + * Copyright (C) 2015 STMicroelectronics ? All Rights Reserved + * + * Author(s): Francesco Virlinzi + * Ajit Pal Singh + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include + +#include + +/* Low Power Timer */ +#define LPC_LPT_LSB_OFF 0x400 +#define LPC_LPT_MSB_OFF 0x404 +#define LPC_LPT_START_OFF 0x408 + +static struct st_clksrc_ddata { + struct clk *clk; + void __iomem *base; +} ddata; + +static void __init st_clksrc_reset(void) +{ + writel_relaxed(0, ddata.base + LPC_LPT_START_OFF); + writel_relaxed(0, ddata.base + LPC_LPT_MSB_OFF); + writel_relaxed(0, ddata.base + LPC_LPT_LSB_OFF); + writel_relaxed(1, ddata.base + LPC_LPT_START_OFF); +} + +static int __init st_clksrc_init(void) +{ + unsigned long rate; + int ret; + + st_clksrc_reset(); + + rate = clk_get_rate(ddata.clk); + + ret = clocksource_mmio_init(ddata.base + LPC_LPT_LSB_OFF, + "clksrc-st-lpc", rate, 300, 32, + clocksource_mmio_readl_up); + if (ret) { + pr_err("clksrc-st-lpc: Failed to register clocksource\n"); + return ret; + } + + return 0; +} + +static int __init st_clksrc_setup_clk(struct device_node *np) +{ + struct clk *clk; + + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) { + pr_err("clksrc-st-lpc: Failed to get LPC clock\n"); + return PTR_ERR(clk); + } + + if (clk_prepare_enable(clk)) { + pr_err("clksrc-st-lpc: Failed to enable LPC clock\n"); + return -EINVAL; + } + + if (!clk_get_rate(clk)) { + pr_err("clksrc-st-lpc: Failed to get LPC clock rate\n"); + clk_disable_unprepare(clk); + return -EINVAL; + } + + ddata.clk = clk; + + return 0; +} + +static void __init st_clksrc_of_register(struct device_node *np) +{ + int ret; + uint32_t mode; + + ret = of_property_read_u32(np, "st,lpc-mode", &mode); + if (ret) { + pr_err("clksrc-st-lpc: An LPC mode must be provided\n"); + return; + } + + /* LPC can either run as a Clocksource or in RTC or WDT mode */ + if (mode != ST_LPC_MODE_CLKSRC) + return; + + ddata.base = of_iomap(np, 0); + if (!ddata.base) { + pr_err("clksrc-st-lpc: Unable to map iomem\n"); + return; + } + + if (st_clksrc_setup_clk(np)) { + iounmap(ddata.base); + return; + } + + if (st_clksrc_init()) { + clk_disable_unprepare(ddata.clk); + clk_put(ddata.clk); + iounmap(ddata.base); + return; + } + + pr_info("clksrc-st-lpc: clocksource initialised - running @ %luHz\n", + clk_get_rate(ddata.clk)); +} +CLOCKSOURCE_OF_DECLARE(ddata, "st,stih407-lpc", st_clksrc_of_register); From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lee Jones Subject: [PATCH v2.1 02/12] clocksource: sti: Provide support for the ST LPC Clocksource IP Date: Tue, 26 May 2015 13:39:43 +0100 Message-ID: <20150526123943.GI11677@x1> References: <1431435500-22899-1-git-send-email-lee.jones@linaro.org> <1431435500-22899-3-git-send-email-lee.jones@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <1431435500-22899-3-git-send-email-lee.jones@linaro.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, daniel.lezcano@linaro.org, tglx@linutronix.de, wim@iguana.be, a.zummo@towertech.it, linux-watchdog@vger.kernel.org, rtc-linux@googlegroups.com, linux@roeck-us.net Cc: kernel@stlinux.com List-Id: devicetree@vger.kernel.org Y2xvY2tzb3VyY2U6IHN0aTogUHJvdmlkZSBzdXBwb3J0IGZvciB0aGUgU1QgTFBDIENsb2Nrc291 cmNlIElQCgpUaGlzIElQIGlzIHNoYXJlZCB3aXRoIFdhdGNoZG9nIGFuZCBSVEMgZnVuY3Rpb25h bGl0eS4gIEFsbCAzIG9mCnRoZXNlIGRldmljZXMgYXJlIG11dHVhbGx5IGV4Y2x1c2l2ZSBmcm9t IG9uZSBhbm90aGVyIGkuZS4gT25seSAxCklQIGNhbiBiZSB1c2VkIGF0IGFueSBnaXZlbiB0aW1l LiAgV2UgdXNlIHRoZSBkZXZpY2UtZHJpdmVyIG1vZGVsCmNvbWJpbmVkIHdpdGggYSBEVCAnbW9k ZScgcHJvcGVydHkgdG8gZW5mb3JjZSB0aGlzLgoKVGhlIFNUIExQQyBDbG9ja3NvdXJjZSBJUCBj YW4gYmUgdXNlZCBhcyB0aGUgc3lzdGVtICh0aWNrKSB0aW1lci4KClNpZ25lZC1vZmYtYnk6IExl ZSBKb25lcyA8bGVlLmpvbmVzQGxpbmFyby5vcmc+CgpkaWZmIC0tZ2l0IGEvZHJpdmVycy9jbG9j a3NvdXJjZS9LY29uZmlnIGIvZHJpdmVycy9jbG9ja3NvdXJjZS9LY29uZmlnCmluZGV4IDY4MTYx ZjcuLjAxYTA3YTYgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvY2xvY2tzb3VyY2UvS2NvbmZpZworKysg Yi9kcml2ZXJzL2Nsb2Nrc291cmNlL0tjb25maWcKQEAgLTI1MCw0ICsyNTAsMTMgQEAgY29uZmln IENMS1NSQ19QWEEKIAloZWxwCiAJICBUaGlzIGVuYWJsZXMgT1NUMCBzdXBwb3J0IGF2YWlsYWJs ZSBvbiBQWEEgYW5kIFNBLTExeDAKIAkgIHBsYXRmb3Jtcy4KKworY29uZmlnIENMS1NSQ19TVF9M UEMKKwlib29sCisJZGVwZW5kcyBvbiBBUkNIX1NUSQorCXNlbGVjdCBDTEtTUkNfT0YgaWYgT0YK KwloZWxwCisJICBFbmFibGUgdGhpcyBvcHRpb24gdG8gdXNlIHRoZSBMb3cgUG93ZXIgY29udHJv bGxlciB0aW1lcgorCSAgYXMgY2xvY2tzb3VyY2UuCisKIGVuZG1lbnUKZGlmZiAtLWdpdCBhL2Ry aXZlcnMvY2xvY2tzb3VyY2UvTWFrZWZpbGUgYi9kcml2ZXJzL2Nsb2Nrc291cmNlL01ha2VmaWxl CmluZGV4IDc1MmQ1YzcuLmUwOGRhNGQgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvY2xvY2tzb3VyY2Uv TWFrZWZpbGUKKysrIGIvZHJpdmVycy9jbG9ja3NvdXJjZS9NYWtlZmlsZQpAQCAtNTEsMyArNTEs NCBAQCBvYmotJChDT05GSUdfQVJDSF9JTlRFR1JBVE9SX0FQKQkrPSB0aW1lci1pbnRlZ3JhdG9y LWFwLm8KIG9iai0kKENPTkZJR19DTEtTUkNfVkVSU0FUSUxFKQkJKz0gdmVyc2F0aWxlLm8KIG9i ai0kKENPTkZJR19DTEtTUkNfTUlQU19HSUMpCQkrPSBtaXBzLWdpYy10aW1lci5vCiBvYmotJChD T05GSUdfQVNNOTI2MF9USU1FUikJCSs9IGFzbTkyNjBfdGltZXIubworb2JqLSQoQ09ORklHX0NM S1NSQ19TVF9MUEMpCQkrPSBjbGtzcmNfc3RfbHBjLm8KZGlmZiAtLWdpdCBhL2RyaXZlcnMvY2xv Y2tzb3VyY2UvY2xrc3JjX3N0X2xwYy5jIGIvZHJpdmVycy9jbG9ja3NvdXJjZS9jbGtzcmNfc3Rf bHBjLmMKbmV3IGZpbGUgbW9kZSAxMDA2NDQKaW5kZXggMDAwMDAwMC4uZjM4Y2YzMwotLS0gL2Rl di9udWxsCisrKyBiL2RyaXZlcnMvY2xvY2tzb3VyY2UvY2xrc3JjX3N0X2xwYy5jCkBAIC0wLDAg KzEsMTIzIEBACisvKgorICogQ2xvY2tzb3VyY2UgdXNpbmcgdGhlIExvdyBQb3dlciBUaW1lciBm b3VuZCBpbiB0aGUgTG93IFBvd2VyIENvbnRyb2xsZXIgKExQQykKKyAqCisgKiBDb3B5cmlnaHQg KEMpIDIwMTUgU1RNaWNyb2VsZWN0cm9uaWNzIOKAkyBBbGwgUmlnaHRzIFJlc2VydmVkCisgKgor ICogQXV0aG9yKHMpOiBGcmFuY2VzY28gVmlybGluemkgPGZyYW5jZXNjby52aXJsaW56aUBzdC5j b20+CisgKgkgICAgICBBaml0IFBhbCBTaW5naCA8YWppdHBhbC5zaW5naEBzdC5jb20+CisgKgor ICogVGhpcyBwcm9ncmFtIGlzIGZyZWUgc29mdHdhcmU7IHlvdSBjYW4gcmVkaXN0cmlidXRlIGl0 IGFuZC9vciBtb2RpZnkKKyAqIGl0IHVuZGVyIHRoZSB0ZXJtcyBvZiB0aGUgR05VIEdlbmVyYWwg UHVibGljIExpY2Vuc2UgYXMgcHVibGlzaGVkIGJ5CisgKiB0aGUgRnJlZSBTb2Z0d2FyZSBGb3Vu ZGF0aW9uOyBlaXRoZXIgdmVyc2lvbiAyIG9mIHRoZSBMaWNlbnNlLCBvcgorICogKGF0IHlvdXIg b3B0aW9uKSBhbnkgbGF0ZXIgdmVyc2lvbi4KKyAqLworCisjaW5jbHVkZSA8bGludXgvY2xrLmg+ CisjaW5jbHVkZSA8bGludXgvY2xvY2tzb3VyY2UuaD4KKyNpbmNsdWRlIDxsaW51eC9pbml0Lmg+ CisjaW5jbHVkZSA8bGludXgvb2ZfYWRkcmVzcy5oPgorI2luY2x1ZGUgPGxpbnV4L3NsYWIuaD4K KworI2luY2x1ZGUgPGR0LWJpbmRpbmdzL21mZC9zdC1scGMuaD4KKworLyogTG93IFBvd2VyIFRp bWVyICovCisjZGVmaW5lIExQQ19MUFRfTFNCX09GRgkJMHg0MDAKKyNkZWZpbmUgTFBDX0xQVF9N U0JfT0ZGCQkweDQwNAorI2RlZmluZSBMUENfTFBUX1NUQVJUX09GRgkweDQwOAorCitzdGF0aWMg c3RydWN0IHN0X2Nsa3NyY19kZGF0YSB7CisJc3RydWN0IGNsawkJKmNsazsKKwl2b2lkIF9faW9t ZW0JCSpiYXNlOworfSBkZGF0YTsKKworc3RhdGljIHZvaWQgX19pbml0IHN0X2Nsa3NyY19yZXNl dCh2b2lkKQoreworCXdyaXRlbF9yZWxheGVkKDAsIGRkYXRhLmJhc2UgKyBMUENfTFBUX1NUQVJU X09GRik7CisJd3JpdGVsX3JlbGF4ZWQoMCwgZGRhdGEuYmFzZSArIExQQ19MUFRfTVNCX09GRik7 CisJd3JpdGVsX3JlbGF4ZWQoMCwgZGRhdGEuYmFzZSArIExQQ19MUFRfTFNCX09GRik7CisJd3Jp dGVsX3JlbGF4ZWQoMSwgZGRhdGEuYmFzZSArIExQQ19MUFRfU1RBUlRfT0ZGKTsKK30KKworc3Rh dGljIGludCBfX2luaXQgc3RfY2xrc3JjX2luaXQodm9pZCkKK3sKKwl1bnNpZ25lZCBsb25nIHJh dGU7CisJaW50IHJldDsKKworCXN0X2Nsa3NyY19yZXNldCgpOworCisJcmF0ZSA9IGNsa19nZXRf cmF0ZShkZGF0YS5jbGspOworCisJcmV0ID0gY2xvY2tzb3VyY2VfbW1pb19pbml0KGRkYXRhLmJh c2UgKyBMUENfTFBUX0xTQl9PRkYsCisJCQkJICAgICJjbGtzcmMtc3QtbHBjIiwgcmF0ZSwgMzAw LCAzMiwKKwkJCQkgICAgY2xvY2tzb3VyY2VfbW1pb19yZWFkbF91cCk7CisJaWYgKHJldCkgewor CQlwcl9lcnIoImNsa3NyYy1zdC1scGM6IEZhaWxlZCB0byByZWdpc3RlciBjbG9ja3NvdXJjZVxu Iik7CisJCXJldHVybiByZXQ7CisJfQorCisJcmV0dXJuIDA7Cit9CisKK3N0YXRpYyBpbnQgX19p bml0IHN0X2Nsa3NyY19zZXR1cF9jbGsoc3RydWN0IGRldmljZV9ub2RlICpucCkKK3sKKwlzdHJ1 Y3QgY2xrICpjbGs7CisKKwljbGsgPSBvZl9jbGtfZ2V0KG5wLCAwKTsKKwlpZiAoSVNfRVJSKGNs aykpIHsKKwkJcHJfZXJyKCJjbGtzcmMtc3QtbHBjOiBGYWlsZWQgdG8gZ2V0IExQQyBjbG9ja1xu Iik7CisJCXJldHVybiBQVFJfRVJSKGNsayk7CisJfQorCisJaWYgKGNsa19wcmVwYXJlX2VuYWJs ZShjbGspKSB7CisJCXByX2VycigiY2xrc3JjLXN0LWxwYzogRmFpbGVkIHRvIGVuYWJsZSBMUEMg Y2xvY2tcbiIpOworCQlyZXR1cm4gLUVJTlZBTDsKKwl9CisKKwlpZiAoIWNsa19nZXRfcmF0ZShj bGspKSB7CisJCXByX2VycigiY2xrc3JjLXN0LWxwYzogRmFpbGVkIHRvIGdldCBMUEMgY2xvY2sg cmF0ZVxuIik7CisJCWNsa19kaXNhYmxlX3VucHJlcGFyZShjbGspOworCQlyZXR1cm4gLUVJTlZB TDsKKwl9CisKKwlkZGF0YS5jbGsgPSBjbGs7CisKKwlyZXR1cm4gMDsKK30KKworc3RhdGljIHZv aWQgX19pbml0IHN0X2Nsa3NyY19vZl9yZWdpc3RlcihzdHJ1Y3QgZGV2aWNlX25vZGUgKm5wKQor eworCWludCByZXQ7CisJdWludDMyX3QgbW9kZTsKKworCXJldCA9IG9mX3Byb3BlcnR5X3JlYWRf dTMyKG5wLCAic3QsbHBjLW1vZGUiLCAmbW9kZSk7CisJaWYgKHJldCkgeworCQlwcl9lcnIoImNs a3NyYy1zdC1scGM6IEFuIExQQyBtb2RlIG11c3QgYmUgcHJvdmlkZWRcbiIpOworCQlyZXR1cm47 CisJfQorCisJLyogTFBDIGNhbiBlaXRoZXIgcnVuIGFzIGEgQ2xvY2tzb3VyY2Ugb3IgaW4gUlRD IG9yIFdEVCBtb2RlICovCisJaWYgKG1vZGUgIT0gU1RfTFBDX01PREVfQ0xLU1JDKQorCQlyZXR1 cm47CisKKwlkZGF0YS5iYXNlID0gb2ZfaW9tYXAobnAsIDApOworCWlmICghZGRhdGEuYmFzZSkg eworCQlwcl9lcnIoImNsa3NyYy1zdC1scGM6IFVuYWJsZSB0byBtYXAgaW9tZW1cbiIpOworCQly ZXR1cm47CisJfQorCisJaWYgKHN0X2Nsa3NyY19zZXR1cF9jbGsobnApKSB7CisJCWlvdW5tYXAo ZGRhdGEuYmFzZSk7CisJCXJldHVybjsKKwl9CisKKwlpZiAoc3RfY2xrc3JjX2luaXQoKSkgewor CQljbGtfZGlzYWJsZV91bnByZXBhcmUoZGRhdGEuY2xrKTsKKwkJY2xrX3B1dChkZGF0YS5jbGsp OworCQlpb3VubWFwKGRkYXRhLmJhc2UpOworCQlyZXR1cm47CisJfQorCisJcHJfaW5mbygiY2xr c3JjLXN0LWxwYzogY2xvY2tzb3VyY2UgaW5pdGlhbGlzZWQgLSBydW5uaW5nIEAgJWx1SHpcbiIs CisJCWNsa19nZXRfcmF0ZShkZGF0YS5jbGspKTsKK30KK0NMT0NLU09VUkNFX09GX0RFQ0xBUkUo ZGRhdGEsICJzdCxzdGloNDA3LWxwYyIsIHN0X2Nsa3NyY19vZl9yZWdpc3Rlcik7CgpfX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2VybmVs IG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDov L2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752802AbbEZMuL (ORCPT ); Tue, 26 May 2015 08:50:11 -0400 Received: from [74.125.82.54] ([74.125.82.54]:36235 "EHLO mail-wg0-f54.google.com" rhost-flags-FAIL-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752641AbbEZMuJ (ORCPT ); Tue, 26 May 2015 08:50:09 -0400 Date: Tue, 26 May 2015 13:39:43 +0100 From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, daniel.lezcano@linaro.org, tglx@linutronix.de, wim@iguana.be, a.zummo@towertech.it, linux-watchdog@vger.kernel.org, rtc-linux@googlegroups.com, linux@roeck-us.net Cc: kernel@stlinux.com Subject: [PATCH v2.1 02/12] clocksource: sti: Provide support for the ST LPC Clocksource IP Message-ID: <20150526123943.GI11677@x1> References: <1431435500-22899-1-git-send-email-lee.jones@linaro.org> <1431435500-22899-3-git-send-email-lee.jones@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1431435500-22899-3-git-send-email-lee.jones@linaro.org> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org clocksource: sti: Provide support for the ST LPC Clocksource IP This IP is shared with Watchdog and RTC functionality. All 3 of these devices are mutually exclusive from one another i.e. Only 1 IP can be used at any given time. We use the device-driver model combined with a DT 'mode' property to enforce this. The ST LPC Clocksource IP can be used as the system (tick) timer. Signed-off-by: Lee Jones diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 68161f7..01a07a6 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -250,4 +250,13 @@ config CLKSRC_PXA help This enables OST0 support available on PXA and SA-11x0 platforms. + +config CLKSRC_ST_LPC + bool + depends on ARCH_STI + select CLKSRC_OF if OF + help + Enable this option to use the Low Power controller timer + as clocksource. + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 752d5c7..e08da4d 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -51,3 +51,4 @@ obj-$(CONFIG_ARCH_INTEGRATOR_AP) += timer-integrator-ap.o obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o +obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o diff --git a/drivers/clocksource/clksrc_st_lpc.c b/drivers/clocksource/clksrc_st_lpc.c new file mode 100644 index 0000000..f38cf33 --- /dev/null +++ b/drivers/clocksource/clksrc_st_lpc.c @@ -0,0 +1,123 @@ +/* + * Clocksource using the Low Power Timer found in the Low Power Controller (LPC) + * + * Copyright (C) 2015 STMicroelectronics – All Rights Reserved + * + * Author(s): Francesco Virlinzi + * Ajit Pal Singh + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include + +#include + +/* Low Power Timer */ +#define LPC_LPT_LSB_OFF 0x400 +#define LPC_LPT_MSB_OFF 0x404 +#define LPC_LPT_START_OFF 0x408 + +static struct st_clksrc_ddata { + struct clk *clk; + void __iomem *base; +} ddata; + +static void __init st_clksrc_reset(void) +{ + writel_relaxed(0, ddata.base + LPC_LPT_START_OFF); + writel_relaxed(0, ddata.base + LPC_LPT_MSB_OFF); + writel_relaxed(0, ddata.base + LPC_LPT_LSB_OFF); + writel_relaxed(1, ddata.base + LPC_LPT_START_OFF); +} + +static int __init st_clksrc_init(void) +{ + unsigned long rate; + int ret; + + st_clksrc_reset(); + + rate = clk_get_rate(ddata.clk); + + ret = clocksource_mmio_init(ddata.base + LPC_LPT_LSB_OFF, + "clksrc-st-lpc", rate, 300, 32, + clocksource_mmio_readl_up); + if (ret) { + pr_err("clksrc-st-lpc: Failed to register clocksource\n"); + return ret; + } + + return 0; +} + +static int __init st_clksrc_setup_clk(struct device_node *np) +{ + struct clk *clk; + + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) { + pr_err("clksrc-st-lpc: Failed to get LPC clock\n"); + return PTR_ERR(clk); + } + + if (clk_prepare_enable(clk)) { + pr_err("clksrc-st-lpc: Failed to enable LPC clock\n"); + return -EINVAL; + } + + if (!clk_get_rate(clk)) { + pr_err("clksrc-st-lpc: Failed to get LPC clock rate\n"); + clk_disable_unprepare(clk); + return -EINVAL; + } + + ddata.clk = clk; + + return 0; +} + +static void __init st_clksrc_of_register(struct device_node *np) +{ + int ret; + uint32_t mode; + + ret = of_property_read_u32(np, "st,lpc-mode", &mode); + if (ret) { + pr_err("clksrc-st-lpc: An LPC mode must be provided\n"); + return; + } + + /* LPC can either run as a Clocksource or in RTC or WDT mode */ + if (mode != ST_LPC_MODE_CLKSRC) + return; + + ddata.base = of_iomap(np, 0); + if (!ddata.base) { + pr_err("clksrc-st-lpc: Unable to map iomem\n"); + return; + } + + if (st_clksrc_setup_clk(np)) { + iounmap(ddata.base); + return; + } + + if (st_clksrc_init()) { + clk_disable_unprepare(ddata.clk); + clk_put(ddata.clk); + iounmap(ddata.base); + return; + } + + pr_info("clksrc-st-lpc: clocksource initialised - running @ %luHz\n", + clk_get_rate(ddata.clk)); +} +CLOCKSOURCE_OF_DECLARE(ddata, "st,stih407-lpc", st_clksrc_of_register);