diff for duplicates of <20150527143648.GA4232@arm.com> diff --git a/a/1.txt b/N1/1.txt index e8b7438..0f2bea6 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,14 +1,14 @@ -Hi André, +Hi Andr?, -On Wed, May 20, 2015 at 05:18:29PM +0100, André Hentschel wrote: -> From: André Hentschel <nerv@dawncrow.de> +On Wed, May 20, 2015 at 05:18:29PM +0100, Andr? Hentschel wrote: +> From: Andr? Hentschel <nerv@dawncrow.de> > > Since commit a4780adeefd042482f624f5e0d577bf9cdcbb760 the user writeable TLS > register on ARM is preserved per thread. > > This patch does it analogous to the ARM patch, but for compat mode on ARM64. > -> Signed-off-by: André Hentschel <nerv@dawncrow.de> +> Signed-off-by: Andr? Hentschel <nerv@dawncrow.de> > Cc: Will Deacon <will.deacon@arm.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > diff --git a/a/content_digest b/N1/content_digest index 8d18680..70e964b 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,28 +1,21 @@ "ref\0555CB3D5.7000307@dawncrow.de\0" - "From\0Will Deacon <will.deacon@arm.com>\0" - "Subject\0Re: [PATCH v2] arm64: Preserve the user r/w register tpidr_el0 on context switch and fork in compat mode\0" + "From\0will.deacon@arm.com (Will Deacon)\0" + "Subject\0[PATCH v2] arm64: Preserve the user r/w register tpidr_el0 on context switch and fork in compat mode\0" "Date\0Wed, 27 May 2015 15:36:48 +0100\0" - "To\0Andr\303\251 Hentschel <nerv@dawncrow.de>\0" - "Cc\0linux-arch@vger.kernel.org <linux-arch@vger.kernel.org>" - Russell King - ARM Linux <linux@arm.linux.org.uk> - linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> - linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> - gregkh@linuxfoundation.org <gregkh@linuxfoundation.org> - Catalin Marinas <Catalin.Marinas@arm.com> - " Nathan Lynch <nathan_lynch@mentor.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" - "Hi Andr\303\251,\n" + "Hi Andr?,\n" "\n" - "On Wed, May 20, 2015 at 05:18:29PM +0100, Andr\303\251 Hentschel wrote:\n" - "> From: Andr\303\251 Hentschel <nerv@dawncrow.de>\n" + "On Wed, May 20, 2015 at 05:18:29PM +0100, Andr? Hentschel wrote:\n" + "> From: Andr? Hentschel <nerv@dawncrow.de>\n" "> \n" "> Since commit a4780adeefd042482f624f5e0d577bf9cdcbb760 the user writeable TLS\n" "> register on ARM is preserved per thread.\n" "> \n" "> This patch does it analogous to the ARM patch, but for compat mode on ARM64.\n" "> \n" - "> Signed-off-by: Andr\303\251 Hentschel <nerv@dawncrow.de>\n" + "> Signed-off-by: Andr? Hentschel <nerv@dawncrow.de>\n" "> Cc: Will Deacon <will.deacon@arm.com>\n" "> Cc: Catalin Marinas <catalin.marinas@arm.com>\n" "> \n" @@ -174,4 +167,4 @@ " \tasm(\n" " \t\"\tmsr\ttpidr_el0, %0\\n\"" -875e74dbf2900afb4919fe90afec6ba98398864f64be2b31164f86bfc18a7645 +9402d9822e7ed736af1b7df51482296ddfd9fb1f6f8c55298d1bcde9258e70fa
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