From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51506) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxwIy-0001ax-ED for qemu-devel@nongnu.org; Thu, 28 May 2015 07:48:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YxwIs-00044X-0y for qemu-devel@nongnu.org; Thu, 28 May 2015 07:48:56 -0400 Received: from mail-bn1bon0068.outbound.protection.outlook.com ([157.56.111.68]:25922 helo=na01-bn1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxwIr-00044T-RP for qemu-devel@nongnu.org; Thu, 28 May 2015 07:48:49 -0400 Date: Thu, 28 May 2015 21:44:52 +1000 From: "Edgar E. Iglesias" Message-ID: <20150528114451.GI27042@toto> References: <1432060414-5195-1-git-send-email-peter.maydell@linaro.org> <1432060414-5195-4-git-send-email-peter.maydell@linaro.org> <20150528053018.GH30952@toto> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH 03/14] target-arm: Set correct syndrome for faults on MSR DAIF*, imm List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Alexander Graf , Sergey Fedorov , Alex =?iso-8859-1?Q?Benn=E9e?= , QEMU Developers , Patch Tracking On Thu, May 28, 2015 at 12:40:42PM +0100, Peter Maydell wrote: > On 28 May 2015 at 09:30, Peter Maydell wrote: > > On 28 May 2015 at 06:30, Edgar E. Iglesias wrote: > >>> @@ -381,6 +381,9 @@ void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm) > >>> */ > >>> if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { > >>> env->exception.target_el = exception_target_el(env); > >>> + env->exception.syndrome = syn_aa64_sysregtrap(0, extract32(op, 0, 3), > >>> + extract32(op, 3, 3), 4, > >>> + 0x1f, imm, 0); > >> > >> Did you possibly reverse the argument order of 0x1f and imm? > > > > Ah, you're right; I was confused because the argument order of our > > syn_aa64_sysregtrap() and the pseudocode AArch64.SystemRegisterTrap > > is different (the latter follows the field order in the syndrome > > register and ours doesn't). > > I also managed to forget the signoff: > Signed-off-by: Peter Maydell > > If this is the only fix in this series (I think you have one or two > patches still left to review) then I propose to add it as I put > the patches in target-arm.next: > > - 0x1f, imm, 0); > + imm, 0x1f, 0); Yes, with these changes: Reviewed-by: Edgar E. Iglesias One of the patches had a missing target_el assigment for CP_ACCESS_TRAP_UNCATEGORIZED that I commented on a while back. I'll have a look again. Thanks, Edgar > > thanks > -- PMM